System and method for testing parameterized logic cores

Details System and method for testing parameterized logic cores System and method for testing parameterized logic cores

2006-04-04

2006-04-04

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S020000, C714S739000, C706S013000

Reexamination Certificate

active

07024345

ABSTRACT:
A system and method for testing a parameterizable logic core are provided in various embodiments. A test controller is configured and arranged to generate a set of random parameter values for the logic core. A netlist is created from the parameterized logic core, and circuit behavior is simulated using the netlist. In other embodiments, selected parameter values are optionally weighted to increase the probability of generating those values, and the parameter set is cloned and mutated when simulation fails.

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