Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-09-01
2002-06-18
Sherry, Michael J. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C714S718000, C714S724000, C702S117000
Reexamination Certificate
active
06407572
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and a method for testing and evaluating (or estimating) a device, such as a LSI (large scale integrated circuit) device, by searching for a factor of defect (i.e., a factor associated with a defect) of the device.
The recent trend in the development and test/evaluation (or estimation) of an LSI device designed by a customer has been toward the demand for a shorter and shorter time for delivering the LSI device to the customer. In order to meet this demand, it is necessary to conduct the test and evaluation of the LSI within a short time in accordance with a test program including the design data and the test data prepared by an EWS (engineering work station) tool, to extract a defective test pattern or defective test condition making up a factor of defect and to feeding the same back quickly to the LSI fabrication and design processes.
2. Description of the Related Art
The development and test/evaluation of an LSI, especially an ASIC (application specific integrated circuit) device designed by the customer are, generally carried out according to the following steps (1) to (7).
(1) The design data of the LSI data are acquired from the customer.
(2) The design data are verified by CAD (computer aided design).
(3) The device data and the test data are prepared based on the design data thus verified.
(4) A test program is produced based on the test data.
(5) The LSI prototype produced based on the design data is evaluated by the test program.
(6) The results of evaluation of the LSI prototype are fed back to the design data and process (fabrication process and design process).
The results of this feedback are used to produce the device data and the test data again, followed by returning to step (4) mentioned above.
(7) The development and the test/evaluation of the LSI device are completed.
In the aforementioned steps of developing and testing/evaluating the LSI device, such as the ASIC device, the design data and the test data are generated automatically using the EWS tool, etc. The persons engaged in the test and evaluation of the LSI device, therefore, can produce a test program without being conscious of the function or the component elements of the circuit. Even the designer of the LSI device is not required to know the contents of the design data from the customer.
As described above, the test and estimation of the LSI device are conducted based only on the state of the test data without using the design data or the CAD data. In the case in which a defective LSI device occurs as a result of a LSI device test, therefore, it is necessary to pinpoint the conditions for making a conforming LSI device by altering the information for setting the testing conditions (pins (terminals), timing, input level, source voltage, etc.). In other words, the defect test pattern or the defect test conditions are required to be fed back to the LSI device fabrication and design processes and to quickly correct any problem points of the design and fabrication processes.
In the test and estimation of the LSI device, the conditions for a conforming LSI device are searched for by altering the testing conditions arbitrarily, and therefore a great amount of time is consumed. In recent years, partly because both the number of terminals (pins) and the density of the LSI have been increasing, the test and evaluation of the LSI device using the LSI testing device (LSI tester) is expected to consume a longer time in the future. While the current trend is toward multiple functions and a higher cost of the LSI testing device as described above, a reduced time length for testing and evaluating the LSI device contributes to a shorter time for accomplishing the development and the test/evaluation of the LSI device.
In actually conducting the test and evaluation of a LSI device, the source voltage, the difference between the simulated test environment and the actual test environment of the LSI device sometimes causes a delicate shift of the source voltage, the input level, the input timing and the output timing from the actual testing conditions.
For this reason, in conducting the test and evaluation of a LSI device or the like according to the conventional method, the conforming (good) or nonconforming (defective) LSI devices are determined while shifting the testing condition for each pin (terminal), and by thus finding out the condition for producing a conforming LSI device, a factor of defect of the device tested has been searched for. In other words, all the pins of the LSI device have been debugged by shifting the testing condition for each pin based on the judgment of the human being.
More specifically, in the conventional test and evaluation method for searching for the conditions for producing a conforming LSI device, a search time required for the search can be simply calculated according to the following formula:
Search time=(Logic verification time per pilot)×(number of pins)×(number of timing edges (TE) per pin)×(number of steps)
For example, the search time for a LSI device having 100 I/O (input/output) pins is determined as follows.
Assuming that the logic verification time per pilot is 100 ms and the logic verification is conducted in 40 steps per ns (nanosecond),
Search
time
=
100
ms
×
100
pins
×
1
TE
×
40
steps
=
4000
pilots
×
100
ms
=
400
seconds
=
6.6
minutes
.
The mainstay of current LSI devices is 300 to 500 pins which is evaluated to consume a search times three to five times (300 to 500 pins) as long as the aforementioned search time. On the other hand, the aforementioned test and evaluation method makes it possible to search for the conditions for a conforming LSI device only in the case in which a defective pin having the factor of defect is only one. In the case in which there are a plurality of defective pins, therefore, the testing conditions are required to be set manually, taking combinations of the testing conditions into consideration in order to search for all the defective pins. This requires a remarkably large number of steps, often making it practically impossible to search for the conditions for a conforming LSI device.
As described above, the time required for searching for the conditions for a conforming LSI device by the conventional device test and evaluation method is so vast that any factor of defect may not be found in the case in which there are a plurality of defective pins. Further, the subjective judgment of the person engaged in this test and estimation requires technical know-how. Consequently, the same evaluation results cannot be easily obtained for every person.
SUMMARY OF THE INVENTION
In view of the problem described above, the object of the present invention is to provide a system and a method for testing and evaluating a device, such as a LSI device, in which the testing conditions can be automatically and quickly altered to search for a factor of defect.
In order to achieve the object described above, according to one aspect of the present invention, there is provided a system for testing and evaluating a device by searching for a factor of defect-thereof, comprising:
a unit for classifying terminals into a plurality of terminal types, based on the information for setting various testing conditions for the device;
a unit for obtaining the data concerning the margin of the testing conditions by altering the testing conditions for each every terminal type; and
a unit for searching for a factor of defect of a specific terminal type in accordance with the data concerning the margin of the testing conditions and detecting a defective terminal from the specific terminal type.
Preferably, in the system according to the present invention, the terminal types include a clock input terminal group, a data input and address input terminal group, a data output te
Kanase Masahiro
Katayama Takayuki
Kikuchi Naoyoshi
Fujitsu Limited
Staas & Halsey , LLP
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