System and method for test generation for system level...

Data processing: measuring – calibrating – or testing – Testing system – Including multiple test instruments

Reexamination Certificate

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C702S118000, C702S120000, C714S010000, C714S011000, C714S012000, C714S025000

Reexamination Certificate

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07472034

ABSTRACT:
A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.

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patent: 6983398 (2006-01-01), Prabhu
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patent: 2006/0276998 (2006-12-01), Gupta et al.
Saha et al., “A Simulation-Based Approach to Architectural Verification of Multiprocessor Systems”, IEEE, 1995, pp. 34-37.

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