System and method for synchronizing divide-by counters

Details System and method for synchronizing divide-by counters System and method for synchronizing divide-by counters

2006-01-24

2006-01-24

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C375S356000

Reexamination Certificate

active

06989696

ABSTRACT:
A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk
signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk
signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk
signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk
signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.

REFERENCES:
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patent: 5317601 (1994-05-01), Riordan et al.
patent: 5638028 (1997-06-01), Voth
patent: 5663687 (1997-09-01), Kozu
patent: 5844436 (1998-12-01), Altmann

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