Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Target device
Reexamination Certificate
2000-05-16
2004-04-06
Broda, Samuel (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Target device
C703S021000, C703S022000, C703S028000, C714S037000, C717S134000, C717S135000
Reexamination Certificate
active
06718294
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to software debuggers and, more particularly, to a method for synchronizing the interaction of multiple debuggers.
BACKGROUND OF THE INVENTION
Embedded systems programming is the development of programs which are intended to be incorporated on a microprocessor that can be included as a part of a variety of hardware devices. Software for embedded systems is typically developed using a single micro-controller or a digital signal processor (DSP) and either an emulation device or a simulation module to which a debugger is attached. A debugger is a tool which aids a programmer or developer in locating and correcting bugs, i.e., errors. In the case of a simulation module, the simulator and the debugger are implemented in software. In the case of an emulation device, the emulation device is a hardware component and the device driver, which is implemented in software, communicates with the debugger.
FIG. 1
shows a prior art single processor simulation environment. As shown in
FIG. 1
, a simulator
100
includes a processor model
110
and a debugger
120
which communicates with the processor model
110
. The debugger
120
is used to display the state of the debug target (i.e., processor model
110
) and to control it, for example, by setting breakpoints or intercepting instructions.
Many embedded software applications are complex and a single micro-processor system, such as the one shown in
FIG. 1
, may not adequately support such complex applications. Multi-processor systems were created to handle these complex systems. Today, integrated circuits are able to integrate the control of the target. A circuit may contain multiple processors as shown in the prior art multi-processor simulation environment of FIG.
2
. Simulator
200
includes three processor models
210
a
,
210
b
and
210
c
. Like the single processor system shown in
FIG. 1
, each processor model
210
a
,
210
b
and
210
c
communicates with a debugger
220
a
,
220
b
and
220
c
, respectively. Control of the processor models
210
a
,
210
b
and
210
c
is handled by a scheduler
230
. It will be appreciated that the scheduler does not exist in the hardware. The scheduler is a simulation artifact. The scheduler's function is to synchronize the computation of multiple simulation models so that it appears as if they are running in parallel. In the hardware environment, the operation of processors is synchronized by a clock signal. The problem with the multi-processor configuration shown in
FIG. 2
is that synchronization is lost when debugging one or more processors in the multi-processor system.
Referring to
FIG. 2
, a loss of synchronization can be illustrated by the following example. As mentioned above, simulator
200
includes three processor models: processor model A
210
a
, processor model B
210
b
and processor model C
210
c
. The processor models
210
a
,
210
b
and
210
c
are run in debug mode using debugger A
220
a
, debugger B
220
b
and debugger C
220
c
, respectively. The debuggers
220
a
,
220
b
and
220
c
each include a display which shows the current location (address) for the execution state of the processor model
210
a
,
210
b
, and
210
c
, respectively. If the debuggers are put into run mode, the debug display, including the address of the current execution instruction, will not be updated until the run mode is suspended, for example by reaching a breakpoint. In this example, the scheduler
230
causes the processor models
210
a
,
210
b
and
210
c
to execute in lock step. For example, in a given clock cycle, processor model A
210
a
will execute an instruction, processor model B
210
b
will execute an instruction and then processor model C
210
c
will execute an instruction. If one of the processors encounters a breakpoint, processing for all three processor models is suspended at the end of the clock cycle. That is, all of the processors that follow the processor which encountered the breakpoint will execute an instruction in order to complete the cycle. For example, if processor model B
210
B encounters a breakpoint, processor model C
210
c
will execute an instruction in order to complete the cycle. Upon reaching a breakpoint, the debug displays update. Therefore, the debug display for processor model B
210
b
will be updated when the breakpoint is encountered. Likewise, the debug display for processor model C
210
c
will be updated. However, the debug display for processor model A
210
a
will not be updated. Therefore, there is a loss of synchronization because the debug displays do not display the proper information to the user, i.e., processor model A
210
a
is not showing the correct address. Thus, a need exists which allows for the debugging of a multi-processor system without the loss of synchronization.
SUMMARY OF THE INVENTION
In accordance with the present invention, a system for debugging a multi-processor environment operates without loss of synchronization. The system can utilize either a simulator or an emulator. The simulator or emulator includes a scheduler in communication with a number of processor models. Each processor model is representative of a processor which will be used in the target environment, for example an integrated circuit. Each processor model communicates with a debug adapter. Preferably, each processor model communicates with a devoted debug adapter. The debug adapters also communicate with the scheduler and with the debuggers. Preferably, each debug adapter communicates with a devoted debugger.
In accordance with another aspect of the present invention, control commands are routed from the debug adapter to the scheduler and other commands are forwarded from the debug adapter to the associated processor model.
In accordance with yet another aspect of the invention, additional modules may be included in the simulator or emulator, for example, a clock gate module.
In accordance with still another aspect of the invention, communications are accomplished using Application Programming Interface (API) calls.
In accordance with a further aspect of the invention, a processor can execute multiple applications concurrently, i.e., one or more processors can multi-task.
REFERENCES:
patent: 5771370 (1998-06-01), Klein
patent: 5805867 (1998-09-01), Kodaira
patent: 5978584 (1999-11-01), Nishibata et al.
patent: 6014512 (2000-01-01), Mohamed et al.
patent: 6356862 (2002-03-01), Bailey
Kalavade et al, “Software Environment for a Multiprocessor DSP”, IEEE Design Automation Conference, pp. 827-830 (Jun. 1999).*
Stoyen et al, “A Language Support Environment for Complex Distributed Real-Time Applications,” Third IEEE International Conference on Engineering of Complex Computer Systems,, pp. 212-221 (Sep. 1997).*
Gabbay et al, “Smart: An Advanced Shared-Memory Simulator—Towards a System-Level Simulation Environment,” IEEE Fifth International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, pp. 131-138 (Jan. 1997).
Broda Samuel
Farjami & Farjami LLP
Mindspeed Technologies Inc.
LandOfFree
System and method for synchronized control of system... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for synchronized control of system..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for synchronized control of system... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3231465