System and method for streamlined execution of instructions

Data processing: software development – installation – and managem – Software program development tool – Translation of code

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717 5, 712 32, 712 37, 712208, G06F 945

Patent

active

060995858

ABSTRACT:
A system and method for the streamlined execution of complex or repeating instructions. The method comprises creating a specialized instruction unit for executing a group of operations and then executing the group as they appear in an instruction stream. The system includes a programmable specialized instruction unit for executing the group of instructions as they appear in an instruction stream. The method comprises receiving a plurality of instructions, examining the plurality of instructions, identifying a subset of the plurality of instructions, creating a specialized instruction unit which is operable to execute the subset, and executing the subset in the special instruction unit upon an occurrence of the subset. Examining the plurality of instructions may occur at such times as compiling a computer program, performing an initialization procedure, or fetching or decoding instructions before execution. Identifying the subset includes selecting a series of instructions which require hardware external to the processor. Creating a specialized instruction unit includes programming a programmable logic or device. The method may also include identifying a second subset of the plurality of instructions, preparing a second specialized instruction unit which is operable to execute the second subset, and executing the second subset in the second specialized instruction unit. The specialized instruction unit is preferably embodied in a computer system comprising a decode unit, a plurality of registers coupled to the decode unit, a load/store unit coupled to the decode unit, a branch execute unit coupled to the decode unit, one or more arithmetic/logic units coupled to the decode unit, one or more specialized instruction units coupled to the decide unit, and a writeback unit coupled to the plurality of registers.

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