Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1999-01-22
2002-04-30
Frejd, Russell W. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C716S030000
Reexamination Certificate
active
06381563
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of computer simulators and more precisely to the field of analog, digital and mixed-signal circuit simulation and modeling.
2. Description of Background Art
Designers of electronic circuits frequently use various techniques to test and modify their designs. One conventional technique is to use computer software to create a circuit design by placing electronic representations of components (component models) in their design. After completing a first design, the design can be simulated to ensure proper functionality. One benefit of simulating circuits before manufacturing is to ensure the circuit functions properly in response to many potential input signals and in a wide variety of operating environments, for example. By identifying and correcting design errors before manufacturing the circuit, a significant savings in terms of both time and expense is achieved.
When modeling and simulating circuits, e.g., analog, digital, or mixed signal circuits, designers attempt to meticulously model the design components, e.g., transistors, resistors, and capacitors, in order to account for the non-ideal nature of the components. For example, in order to more accurately model components, intrinsic capacitances and resistances should be included. Designers also use a hierarchical structure to more efficiently design a circuit. This permits a single element, or a group of elements to be described as a subcircuit, for example, which can be used many times but whose definition need only be stored in memory once. Another benefit of using hierarchical structures is that it presents a more abstract view at any hierarchical level, allowing the designer to concentrate on the interface at that level, without worrying about the detail which is at a lower level.
FIG. 1
is an illustration of a filter subcircuit that can be used in designing circuits. The filter subcircuit definition is denoted as S
1
and is defined as part of a second level of the design hierarchy. The filter subcircuit S
1
includes a resistor R
1
and a capacitor C
1
combined in the orientation illustrated in FIG.
1
. The resistor R
1
and capacitor C
1
are defined in a first level of the design hierarchy. In order to simplify the design process, the designer can use the filter subcircuit instead of the lower level components, e.g., R
1
and C
1
. This simplifies the design and decreases memory requirements since R
1
and C
1
need only be stored once and one or more references to the subcircuit in the second level will reference these components. For example, subcircuit S
1
may be defined in a design language, such as SPICE, as
.SUBCKT S
1
A B
R
1
A B
1
K
C
1
B 0
1
U
.ENDS
where the subcircuit definition name or label is S
1
, and it is defined as including (1) a resistor labeled R
1
that is located between nodes A and B and (2) a capacitor labeled C
1
that is located between node B and ground (0). Additional elements or modeling can be included and would be apparent to persons skilled in the art. Additional details regarding the operation of SPICE are described in R. Kielkowski
SPICE, Practical Device Modeling
, McGraw-Hill (1995), which is incorporated by reference herein in its entirety.
FIG. 2
is an illustration of a hierarchical circuit design using three instances of (references to) filter subcircuits. In some hierarchical design systems, a subcircuit label, e.g., X
2
, can only be used once at each level of the hierarchy. However the same label, tag, or name can be used at different hierarchical levels. In
FIG. 2
, different subcircuit instances are labeled with different names. Three second level subcircuit instances, X
1
, X
2
, and X
3
are all defined to be of a type S
1
, as illustrated in FIG.
1
. These second level subcircuits are in hierarchical level 2 and are serially combined to form a third level subcircuit that is labeled S
2
. The S
2
subcircuit could be defined as:
.SUBCKT S
2
in out
X
1
in A S
1
X
2
A B S
1
X
3
B out S
1
.ENDS
where subcircuit S
2
is defined as including (1) an instance X
1
that is located between the input (in) and node A and is a subcircuit as defined by S
1
at the previous hierarchical level, (2) another instance of a subcircuit of the type S
1
that is labeled X
2
and is located between nodes A and B, and (3) a third instance of a subcircuit of the type S
1
that is located between nodes B and out. In some hierarchical design systems, a subcircuit instance label must begin with the letter “X” (or “x”), though this is not true of all hierarchical design systems and is not required for the present invention. For ease of discussion, in this section subcircuits instance labels will begin with “X”.
FIG. 3
a
is an illustration of a circuit design at the third hierarchical level.
FIG. 3
b
is an illustration of a circuit design of
FIG. 3
a
at the first hierarchical level. In order to design a circuit having six filters a designer who has access to subcircuit S
2
in the third hierarchical level can design the circuit merely by placing two subcircuit instances X
1
and X
2
that are defined to be of an S
2
subcircuit type as illustrated in
FIG. 3
a
. The circuit illustrated in
FIG. 3
a
is equivalent to the circuit illustrated in
FIG. 3
b
. However, by using subcircuits and hierarchical design techniques, the designer can focus on the high level functions instead of the lower level details. The code representing
FIG. 3
a
can be:
X
1
in A S
2
X
2
A out S
2
where X
1
is a subcircuit of the type S
2
(in the previous hierarchical level) and is located between nodes “in” and “A”. X
2
is also a subcircuit of the type S
2
and is located between nodes “A” and “out”.
A problem with conventional hierarchical designs is that while a designer can design at various hierarchical levels to avoid implementation details, when the designer wants to test the design by simulating it, the designer must address the implementation details. In the above example, in order to identify the current through the third resistor in the first hierarchical level, i.e., Ixy in
FIG. 3
b
, the designer must know where the resistor is in the hierarchy and must identify each hierarchical level in order to determine the simulated element, e.g., the current through resistor X
1
.X
3
.R
1
. Accordingly, in order to save the current through the third resistor of
FIG. 3
b
during simulation the designer must program the following statement (given in Spectre circuit simulator syntax, Spectre is commercially available from Cadence Design Systems, Inc., San Jose, Calif.):
save X
1
.X
3
.R
1
:i
which identifies subcircuit X
1
in the third hierarchical level, then identifies subcircuit X
3
in the second hierarchical level and then identifies R
1
in the first hierarchical level before requesting the current (i) through the resistor be saved, see
FIGS. 1
,
2
, and
3
a.
Subcircuit definitions can also contain parasitic components. Subcircuit definitions can be parameterized, and include models, and the subcircuit parameters can be referenced in expressions in the models and/or parasitic components, for example.
In addition, a problem with conventional models is that the output parameters are predefined. Currently, a designer has no efficient technique for modifying the output parameters of the models.
What is needed is a system and method for modeling and simulating circuits that (1) reduces the hierarchy from the perspective of the circuit designer; (2) more efficiently models parasitic components; (3) more efficiently parameterizes device models; (4) more effectively creates models that are compatible with other simulation tools; (5) can change the interface of a component without requiring the designer to use an extra layer of hierarchy; (6) provides a more efficient interface by hiding details from the designer; (7) enables hidden monitors and other functional designs to be automatically simulated by hiding these functions from the designer in a design level that is below the design level that is o
Ghijsen Walter J.
Kundert Kenneth S.
O'Riordan Donald J.
Cadence Design Systems Inc.
Frejd Russell W.
Lyon & Lyon LLP
LandOfFree
System and method for simulating circuits using inline... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for simulating circuits using inline..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for simulating circuits using inline... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2845502