Patent
1996-09-12
1999-01-19
Teska, Kevin J.
3951831, 395733, G06F 1310
Patent
active
058623663
ABSTRACT:
A multiprocessing system comprising a plurality of processors and a plurality of I/O devices. A central interrupt control unit functionally intercouples the plurality of processors and I/O devices. The central interrupt control unit is configured to receive interrupt signals from the I/O devices and is configured to distribute interrupt signals to the processors. One of the processors is configured as a master test processor to control a test mode for testing the central interrupt control unit. The master test processor is further configured to release the other processors and emulate a multiprocessing environment.
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Ennis Steve
Schmidt Rodney
Wisor Michael T.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Phan Thai
Teska Kevin J.
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