Electrical computers and digital processing systems: multicomput – Multicomputer data transferring via shared memory
Reexamination Certificate
2002-12-13
2004-09-21
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: multicomput
Multicomputer data transferring via shared memory
C711S141000
Reexamination Certificate
active
06795850
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to distributed shared memory systems and, more particularly, to a memory mapping scheme for use in a distributed shared memory system.
2. Description of the Related Art
Wide varieties of storage devices are used in modern computer systems. Such storage devices include individual hard drives, storage arrays, and tape drives. Each type of storage device may have an associated storage controller that controls how that storage device is accessed by a host computer. For example, a hard drive typically includes an integrated storage controller that controls how a hard disk included in that hard drive is accessed. A storage array may include several hard drives and one or more storage controllers that each control how individual hard drives within the storage array are accessed.
Often, storage controllers include a write cache that temporarily buffers data being written to a storage device by a host computer. A write cache may be accessed more quickly than a larger non-volatile storage media within the storage device, allowing a storage controller to handle a write access more quickly than if the write was actually performed to the storage media. Furthermore, if the data is subsequently requested again before being written from the write cache to the non-volatile storage media, the storage controller may more quickly provide the data to the host computer from the write cache than it could from the non-volatile storage media. However, using a write cache may also lead to increased data vulnerability. For example, most storage controllers acknowledge completion of a write access after buffering the write data in the write cache, even though the write data has not actually been written to the non-volatile storage media. If the storage controller experiences a failure before the write data is written to the non-volatile storage media, that data may be lost.
In order to provide protection against data losses due to write cache failures, some storage controllers implement write-cache mirroring techniques. For example, two array controllers may control access to a storage array. If one of the array controllers receives write data, that array controller may generate a write access to the other array controller's write cache so that both array controller's write caches contain the same write data. Accordingly, if one array controller fails, the other array controller's write cache will still have a valid copy of the data. In order to make sure that copies of the write data are mirrored in both write caches, an array controller may not acknowledge the write access until the cache mirroring is complete.
While cache mirroring may provide improved reliability, it may also have detrimental effects on storage device performance. For example, the time required to communicate the mirrored cache write may substantially increase the time required to perform a write access. Additionally, such cache mirroring techniques may consume an undesirable amount of bandwidth, both within each storage controller (e.g., processor intervention is typically needed to generate an external I/O operation) and on an external communication link coupling the storage controllers (e.g., this link is typically the link used to couple the storage controllers to the storage devices).
Write cache coherency is an additional concern that arises when using cache mirroring techniques. If different storage controllers are caching different versions of the same data, a write access to that data may return stale data unless there is some way of determining which storage controller is caching the most recent version of the data. Furthermore, performing such a determination may itself decrease performance. These concerns are typical of distributed shared memory (DSM) systems in which processing devices share access to each other's memories and copies of the same data may exist in multiple memories.
Accordingly, it is desirable to be able to provide new cache mirroring techniques for use in storage controllers and to provide new ways of controlling access to shared data in DSM systems, particularly those involving storage controllers.
SUMMARY
Various embodiments of systems and methods for sharing memory between nodes may involve implementing a communication protocol for reflecting memory access requests. Each node's memory controller may be configured to send and receive messages on a dedicated memory-to-memory interconnect according to the communication protocol and to responsively perform memory accesses in a local memory. The type of message sent on the interconnect may depend on which memory region is targeted by a memory access request local to the sending node. If certain regions are targeted locally, a memory controller may delay performance of a local memory access until the memory access has been performed remotely. Remote nodes may confirm performance of the remote memory accesses via the memory-to-memory interconnect.
In one embodiment, a system may include several nodes, which each include a memory controller coupled to a respective memory, and an interconnect coupling the nodes'memory controllers. An initiating memory controller in one of the nodes is configured to send a semaphore region write request via the interconnect. In response to receiving the semaphore region write request via the interconnect, each other memory controller is configured to perform a write access to an otherwise read-only portion of a semaphore region of the respective memory. In response to receiving an indication that the other memory controller has performed the write access, the initiating memory is configured to perform the write access to a writeable portion of the respective memory.
One embodiment of a method may involve: a memory controller receiving a request to perform a write access in a local memory via a first interconnect; dependent upon an address of the write access specified in the request, the memory controller forwarding the request to at least one other memory controller via a second interconnect, where each of the other memory controllers is coupled to a respective memory; and the memory controller delaying performance of the write access in the local memory until receipt of an indication that each of the other memory controllers have completed the write access.
In some embodiments, a storage device controller may include: a host interface to a host computer system; a local interconnect coupled to the host interface; a processing device coupled to the local interconnect; a memory controller coupled to the local interconnect; and a memory coupled to the memory controller. The memory controller includes an interface to a memory-to-memory interconnect. In response to the host interface receiving a host write request from the host computer system, the processing device is configured to convey a write access request to the memory controller via the local interconnect. In response to receiving the write access request, the memory controller is configured to communicate an indication of the write access request via the memory-to-memory interconnect dependent upon an address within the memory targeted by the write access request. Further dependent upon the address within the memory targeted by the write access request, the memory controller is configured to delay performance of a write access requested by the write access request until the memory controller receives an indication of remote completion of the write access.
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“Sun Storeddge
Acton John D.
Wu Chia Y.
Kowert Robert C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Moazzami Nasser
Sun Microsystems Inc.
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