Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Patent
1996-06-14
1998-07-07
Young, Brian K.
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
H03M 900
Patent
active
057775672
ABSTRACT:
A serial data to parallel data converter is disclosed which has the advantage of accurately converting high frequency serial data to parallel data while using clock signals operating at a relatively low frequency. A low bit error rate is achieved by avoiding the use of multiple high speed clock lines typically found in other converters. The simplified circuit design also has the advantage of requiring minimal semiconductor layout area and reduced power requirements. One embodiment includes a buffer, a first data delay line, coupled to receive serial data from the buffer, and a phase lock loop (PLL), coupled to receive serial data from the buffer. A second data delay line is configured as a voltage controlled oscillator (VCO) within the PLL. The PLL locks onto the incoming serial data signal and provides a control signal back to the first data delay line to ensure it is storing serial data bits as they arrive. After n-bits of data have been transmitted the first data delay line contains a n-bit wide parallel word.
REFERENCES:
patent: 5164724 (1992-11-01), Hartley
Bosnyak Robert J.
Drost Robert J.
Murata David M.
Hauser Robert Scott
Sun Microsystems Inc.
Young Brian K.
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