Pulse or digital communications – Transceivers
Reexamination Certificate
1999-09-09
2002-10-08
Pham, Chi (Department: 2631)
Pulse or digital communications
Transceivers
C375S220000, C375S244000, C375S257000, C375S293000, C375S354000, C375S355000, C375S360000, C370S284000, C370S301000
Reexamination Certificate
active
06463092
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application is a utility conversion of U.S. Pat. No. 60/099,770, entitled “Embedded Back Channel For TMDS” by Gyudong Kim, filed Sep. 10, 1998.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of data communications, and more particularly, to the transmission of clock and data signals. Still more particularly, the present invention relates to the transmission of clock signals and data signals on the same transmission line in transition minimized differential signaling (TMDS) system.
2. Description of the Background Art
There are a variety of prior art systems and method for transmitting data between a transmitter and a receiver. Various serial links and other methods for transmitting data and clock signals are well known. However, most such schemes provide a single line or channel dedicated for the transmission of the clock signals and other signal lines or channels dedicated for the transmission of data. Once such system is described by Kyeongho Lee, Sungjoon Kim, Gijung Ahn, and Deog-kyoon Jeong in “A CMOS Serial Link For Fully Duplexed Data Communication,” IEEE Journal of Solid State Circuits, Vol. 30, No. pp. 353-364, April 1995.
The present invention will be discussed in the context of transition minimized differential signaling (TMDS), however, those skilled in the art will recognize that the present invention is applicable in various other data communication contexts. In TMDS, four signal lines are provided, and each signal line is preferably a differential pair. One signal line is a for a low speed clock signal and the three other signal lines are for high-speed data transmission.
One important aspect of all data communication systems is to maximize the bandwidth provided by the data. channels. However, most systems include a variety of control signals that must be sent between the transmitter and the receiver to ensure proper operation, and maintain synchronization between the transmitter and the receiver. For example, it is not uncommon for as much as 20% of the bandwidth to be used for framing and synchronization in serial communication. One problem is that the bandwidth available for data is typically reduced because the data signal lines must be used to transmit these control signals between the transmitter and receiver. Yet another problem is latency in transmitting the control signals to the recipient. Especially in video data communication, much of the data must be transmitted in blocks during which control signals cannot be sent. For example, when transmitting data from a controller to a flat panel, the data is transmitted, and then there is a data enable period corresponding to the blanking period in CRT display that is used to send control and synchronization signal. Only during that data enable period can the control signals be sent under most protocols. Therefore, there is latency imposed on transmitting control signals to the receiver. Thus, there is need for a system that can provide for control signaling between the transmitter and the receiver without decreasing the available bandwidth for data transfer, and while reducing the latency in sending control signals.
Yet another problem in the prior art is that most systems do not provide a mechanism to get signals from the receiver back to the transmitter. In other words, there is not a return channel for communication. Some systems have provided additional signal lines, however, their addition and interface add significant complication, require re-wiring and create other problems that make the addition of a physical line unworkable. Another approach is to add a second transmitter, second receiver and signal lines. However, this essentially doubles the hardware requirements making such a solution too expensive. Furthermore, such duplication is overkill for the amount of data that needs to be sent between the transmitter and the receiver, especially when the application is one of sending video data from a transmitter to a receiver such as communication between a graphic controller and a video display device.
Therefore, there is a need for a system and method for that uses the clock signal line also for transmitting data signals between the transmitter and the receiver and vice-versa.
SUMMARY OF THE INVENTION
The present invention overcomes the deficiencies and limitations of the prior art with a unique data communication system. The system preferably includes a unique transmitter and receiver coupled by a transmission line. The transmitter sends both a clock signal and data signals over the transmission line to the receiver. The receiver uses the same transmission line to send data signals back to the transmitter.
The transmitter preferably comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data in addition to the clock signal. The line interface couples the output of the clock generator to the transmission line. The line interface also couples the transmission line to the decoder and in doing so removes the signals from the clock generator. The decoder receives the signals from the line interface and decodes the signal to determine the data being sent from the receiver to the transmitter on the same line used to send the clock and data from the transmitter to the receiver.
The receiver preferably comprises a line interface, a clock re-generator, a data decoder and a return channel encoder. The clock re-generator, the data decoder and the return channel encoder are coupled to the transmission line by the line interface. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The data decoder similarly is coupled to receive the signals on the transmission line, and filters and decodes the signals to produce data signals. This is preferably done by determining the position of the falling edge of the clock signal and translating the falling edge position into bit values. In contrast, the return channel encoder generates signals and asserts them on the transmission line. These signals are asserted or superimposed over the clock & data signals provided by the transmitter.
These and other features and advantages of the present invention may be better understood by considering the following detailed description of a preferred embodiment of the invention. In the course of this description, reference will frequently be made to the attached drawings.
REFERENCES:
patent: 4459591 (1984-07-01), Haubner et al.
patent: 5577071 (1996-11-01), Gehrke et al.
patent: 0 798 901 (1997-10-01), None
patent: 2 251 139 (1975-06-01), None
“Phase Modulation I/O Interface Circuit”; Kazutaka Nogami et al.; IEEE International Solid-State Circuit Conference; vol. 37 Feb. 1994 (New York, US); 3 pages.
Loinaz, Marc J., Wooley, Bruce A., “A BiCMOS Time Interval Digitizer for High-Energy Physics Instrumentation”, Center for Integrated Systems, Stanford University, IEEE 1993 Custom Integrated Circuits Conference, pp. 28.6.1-28.6.4.
Hwang Seung Ho
Kim Gyudong
Kim Min-Kyu
Hickman Paul
Kelley Steve S.
Perkins Coie LLP
Pham Chi
Silicon Image Inc.
LandOfFree
System and method for sending and receiving data signals... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for sending and receiving data signals..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for sending and receiving data signals... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2987071