System and method for selecting shorted wordlines of an array ha

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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365200, 36518523, 36523004, G11C 800

Patent

active

058986375

ABSTRACT:
A memory system including an array of memory cells connected along wordlines and bitlines, wordline driver circuitry for driving at least two selected wordlines simultaneously in response to multirow selection bits, and selection bit circuitry for asserting multirow selection bits to the wordline driver circuitry in response to address bits (or address bits and control bits) to cause simultaneous selection of a target wordline and at least one other wordline shorted with the target wordline, and wordline selection methods performed by such a system. Preferably, the selection bit circuitry includes a predecoder implemented as a logic circuit, and the wordline driver circuitry includes a row decoder, a set of wordline drivers for driving even-numbered wordlines, and another set of wordline drivers for driving odd-numbered wordlines. The predecoder preferably includes an odd wordline predecoder for asserting selection bits for selecting at least one odd wordline of an erase block, and an even wordline predecoder for asserting selection bits for selecting at least one even wordline of the erase block. The system preferably includes a controller which generates a set of address bits for selecting a target wordline, and registers which store control bits which can be accessed by the predecoder to determine the predecoder's mode of operation. The invention allows shorted wordlines to be selected simultaneously during a programming operation (preliminary to an erase operation), to prevent the wordline supply from shorting to ground during the programming operation.

REFERENCES:
patent: 5602778 (1997-02-01), Futatsuya et al.
patent: 5615163 (1997-03-01), Sakui et al.
patent: 5629898 (1997-05-01), Idei et al.

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