System and method for scaleable encoding and decoding of variabl

Details System and method for scaleable encoding and decoding of variabl System and method for scaleable encoding and decoding of variabl

1997-08-14

2000-04-25

Williams, Howard L.

Coded data generation or conversion

Digital code to digital code converters

To or from minimum d.c. level codes

341100, 370476, H03M 700, H04J 300

Patent

active

060549424

ABSTRACT:
A method and system for parallel encoding of data for bit-stuffed HDLC compatible transmission is presented. The method analyses a byte in parallel with four recirculated previously encoded bits during each clock cycle. The recirculated bits allow for correct analysis of the presence of a fifth consecutive one within the byte including the first four bits thereof. The encoded byte is provided to a FIFO and, when 8 bits are stored therein, the eight most significant bits are extracted from the FIFO for transmission via a digital or analogue network. The FIFO provides two bytes without receiving an intervening encoded data byte when a risk of an overflow exists.

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William Stallings, Data and Computer Communications, 5th Edition, Prentice Hall, 1997,copyright 1997, pp. 216-218.
Anonymous, Parallel Architecture for High Speed Bit Stuffing and Byte Alignment, IBM Technical Disclosure Bulletin vol. 32, No. 6B Nov. 1989 pp. 31-34.

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