System and method for row decode in a multiport memory

Details System and method for row decode in a multiport memory System and method for row decode in a multiport memory

2003-02-10

2004-12-21

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S756000

Reexamination Certificate

active

06833624

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to computer memories, and more particularly to a row decode having overlapping predecode wires in a multiport memory.
2. Description of the Related Art
Currently, random access memory (RAM) architectures include an array of memory cells, arranged as rows and columns, with each cell storing one bit of information. As is well known, the rows are accessed using wordlines and the columns are accessed via bitlines. Generally, storage capacity and operational speed of the memory are important attributes for systems requiring memory devices. Storage capacity refers to the amount of data that a memory device can store, and operational speed refers to the speed at which the memory device can store or retrieve data.
System access speed can often be dramatically increased through the use of mutliport memory architectures having two or more access ports. For example, a dual port memory has two access ports, allowing more than one system device to directly access the memory. In contrast, a single port memory permits direct coupling to only one system device, and as a result, other system devices must contend for the port to gain access to the memory. By permitting direct coupling to more than one system device, overall system performance is usually enhanced.
FIG. 1
is a block diagram showing a conventional multiport memory
100
. The multiport memory
100
includes a multiport core array
102
coupled to a write port
104
for data input, and a read port
106
having sense amplifiers and output circuitry for data output. Also included are read wordline drivers
108
coupled to read control circuitry
114
, and write wordline drivers
110
coupled write control circuitry
112
. To address the read wordline drivers
108
, a read row decode
116
coupled to predecode circuitry
118
is included. Similarly, to address the write wordline drivers
110
, a write row decode
120
coupled to predecode circuitry
122
is included.
As shown in
FIG. 1
, the read row decode
116
and the write row decode
120
each including a plurality of predecode wires that are utilized to address the read wordline drivers
108
and the write wordline drivers
110
. More specifically, each predecode wire of the row decode units
116
and
120
is connected to a particular row of the wordline drivers
108
or
110
. In addition, several predecode wires can be coupled to an AND gate. to facilitate addressing. Unfortunately, to ensure the predecode wires are separately addressable, conventional multiport memories
100
include a large amount of whitespace surrounding the predecode wires of the row decode units
116
and
120
.
In view of the foregoing, there is a need for port predecode circuitry with reduced area requirements. Specifically, the port predecode circuitry should allow proper addressing of port wordline drivers, while requiring less area for the predecode wires of the port predecode circuity.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing an overlapping row decode that reduces the area required for wordline row decode in multiport memories. In one embodiment, a method for making a row decode in a multiport memory is disclosed. A first plurality of predecode wires is formed on a first metalization layer. The first plurality of predecode wires is configured to address wordline drivers of a first port. A plurality of wordline connections is formed on a second metalization layer above the first metalization layer, where the wordline connections are portioned into two portions. A first portion of the plurality of the wordline connections is in communication with both the wordline drivers of the first port and the first plurality of predecode wires. A second plurality of predecode wires is formed on a third metalization layer above the second metalization layer. The second plurality of predecode wires is configured to address wordline drivers of a second port. The second plurality of predecode wires is in communication with the second portion of wordline connections, which are further in communication with the wordline drivers of the second port. Optionally, the second plurality of predecode wires can overlap the first plurality of predecode wires. Also optionally, the first metalization layer can be an m
1
layer, the second metalization layer can be an m
2
layer, and the third metalization layer can be an m
3
layer.
In an additional embodiment, a multiport memory is disclosed. The multiport memory includes a first plurality of predecode wires positioned on a first metalization layer. The first plurality of predecode wires is configured to address wordline drivers of a first port. In addition, a second plurality of predecode wires is located on a third metalization layer above the first metalization layer. The second plurality of predecode wires is configured to address wordline drivers of a second port. The multiport memory further includes a plurality of wordline connections that are formed on a second metalization layer between the first metalization layer and the third metalization layer. As above, the plurality of wordline connections includes a first portion and a second portion. The first portion of the plurality of wordline connections is in communication with the first plurality of predecode wires and the wordline drivers of the first port. The second portion of the plurality of wordline connections is in communication with the second plurality of predecode wires and the wordline drivers of the second port. As above, the second plurality of predecode wires can overlap the first plurality of predecode wires. In one aspect, the second plurality of predecode wires can be skewed from the first plurality of predecode wires. Typically, the first plurality of predecode wires, the second plurality of predecode wires, and the plurality of wordline connections can form a first overlapping row decode unit. In this case, the multiport memory can include a second overlapping row decode unit that is used in conjunction with the first overlapping row decode unit to address the first port and second port.
A generator for generating a row decode in a multiport memory is disclosed in a further embodiment of the present invention. The generator includes logic that generates, on a first metalization layer, a first plurality of predecode wires that is configured to address wordline drivers of a first port. In addition, logic is included that generates a plurality of wordline connections on a second metalization layer above the first metalization layer. A first portion of the plurality of the wordline connections is in communication with the wordline drivers of the first port and the first plurality of predecode wires. The generator further includes logic that generates a second plurality of predecode wires on a third metalization layer above the second metalization layer. The second plurality of predecode wires is configured to address wordline drivers of a second port. In addition, the second plurality of predecode wires is in communication with a second portion of the plurality of wordline connections, which are further in communication with the wordline drivers of the second port. As above, the second plurality of predecode wires can overlap the first plurality of predecode wires. In addition, the generator can include logic that interleaves the predecode wires. In this aspect, the generator includes logic that generates a fourth plurality of predecode wires, on the third metalization layer, which is configured to address wordline drivers of the first port. In addition, logic can be included that generates a fifth plurality of predecode wires on the first metalization layer. The fifth plurality of predecode wires is configured to address wordline drivers of the second port. Further, logic can be included that connects the first portion of the plurality of the wordline connections to the fourth plurality of predecode wires, and logic that connects the second portion of the pluralit

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