System and method for routing supply voltages or other...

Details System and method for routing supply voltages or other... System and method for routing supply voltages or other...

2008-09-24

2010-06-29

Nguyen, Ha Tran T (Department: 2829)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C257S678000, C257S690000

Reexamination Certificate

active

07745263

ABSTRACT:
An integrated circuit or chip includes a first die and a second die positioned on a lead frame of a package including a lead frame, such as a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame. The integrated circuit further includes a redistribution layer formed on the first die to couple selected bond fingers of the lead frame to selected bonding pads of the first and second die. The selected bond fingers may correspond to bond fingers that receive a first supply voltage or the first supply voltage and a second supply voltage.

REFERENCES:
patent: 5325268 (1994-06-01), Nachnani et al.
patent: 5552966 (1996-09-01), Nagano
patent: 5625235 (1997-04-01), Takiar
patent: 7148567 (2006-12-01), Moriguchi et al.
patent: 2002/0123186 (2002-09-01), Mayama et al.
patent: 2005/0156305 (2005-07-01), Moriguchi et al.
patent: 2007/0128821 (2007-06-01), Lee et al.

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