System and method for robust clocking schemes for logic circuits

Details System and method for robust clocking schemes for logic circuits System and method for robust clocking schemes for logic circuits

1997-04-21

1999-04-13

Teska, Kevin J.

Boots, shoes, and leggings

364489, G06F 1750

Patent

active

058944192

ABSTRACT:
A system and method according to the present invention for mapping a clocking scheme to determine robust clocking schemes in a logic circuit is disclosed. The circuit can be represented by a clocking graph, the clocking graph having at least one loop including a plurality of vertices, wherein two vertices represent each relevant signal, one for a rising edge and one for a falling edge. Additionally, a plurality of constraints of the logic circuit propagate through circuit delays. The method according to the present invention comprises the steps of selecting one of the vertices as a reference; assigning at least one of the plurality of vertices as an unknown; creating at least a first equation by setting the unknown as not equal to any of the other vertices for each constraint, the first equation being included in a set of equations; creating at least a second equation by setting a sum of times between edges equal to a number of phases in a cycle, the second equation representing the at least one loop in the clocking graph, wherein the second equation is also included in the set of equations; and solving the set of equations to provide a set of clocking schemes.

REFERENCES:
patent: 5461576 (1995-10-01), Tsay et al.
patent: 5644499 (1997-07-01), Ishii
patent: 5663888 (1997-09-01), Chakradhar
patent: 5740347 (1998-04-01), Avidan
patent: 5764951 (1998-06-01), Ly et al.
patent: 5774370 (1998-06-01), Giomi

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