Oscillators – Combined with particular output coupling network
Reexamination Certificate
2001-12-10
2004-08-03
Mis, David (Department: 2817)
Oscillators
Combined with particular output coupling network
C331S075000, C331S1160FE, C331S158000, C331S175000, C327S175000, C327S295000
Reexamination Certificate
active
06771136
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a clocking circuit for synchronizing an electronic subsystem and, more particularly, to a circuit for regulating the mark/space ratio (or “duty cycle”) of a clocking signal produced by an oscillator and fed to the electronic subsystem.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Within nearly every electronic subsystem that relies upon sequential operations, it is essential to have an oscillator or waveform generator of some sort. The oscillator functions to produce a periodic waveform, and that waveform serves as a source of regularly spaced pulses, alternatively known as a “mark.” Pairs of marks are separated by a “space.”
There are numerous types of oscillators used to generate clocking signals for electronic subsystems. Popular oscillators include RC oscillators or LC oscillators which are fairly stable at relatively high frequencies. However, for much greater stability at even higher frequencies, crystal oscillators are used.
A crystal oscillator involves a piece of quartz that vibrates at a certain frequency. The quartz crystal can, therefore, be a central element in numerous types of oscillators, such as the Pierce oscillator or the Colpitts oscillator. As the quartz oscillates, the quartz output can be brought to a particular logic level by circuitry connected to the quartz output.
In addition to the Pierce and Colpitts oscillators, another popular oscillator is the Complimentary Metal Oxide Semiconductor (“CMOS”) inverter oscillator. This oscillator generally involves an inverter placed in parallel to the quartz crystal. Depending on the RLC model of the oscillator, resistors and capacitors may also be coupled in parallel or series to the quartz and CMOS inverter.
In most instances, the output of the oscillator must drive one or more distally located electronic subsystems. If an electronic subsystem has a rather substantial clock signal load, the output of the oscillator must be buffered. A buffer can, therefore, present a constant load impedance to the oscillator, yet drive possibly numerous clocking signal loads or electronic subsystems. The buffer, thereby, serves to isolate the impedance change applicable to those subsystems from the oscillator and, thereby, stabilizes the oscillator load.
FIG. 1
illustrates an example of a CMOS crystal oscillator
10
and a buffer
12
. The quartz crystal
14
may be selected to oscillate at a particular frequency, and that frequency is perpetuated and maintained at a particular logic level by inverter
16
. The output from inverter
16
is a periodic waveform that has a voltage amplitude sufficient to drive buffer
12
. In the example shown, the oscillator output (V
OSC
) is a sine wave
18
. Oscillator
10
output need not, however, be a sine wave, yet if the p- and n-channel transistors of inverter
16
are relatively weak, then a sine wave is achieved. Depending on the strength of the inverter
16
, the ramp up and ramp down (leading and trailing edges) of each waveform transition can change.
Buffer
12
can be made of any circuitry which isolates the impedance of electronic subsystem
20
from oscillator
10
. One example of a buffer might be an inverter or a number of inverters, depending on the needed logic value at the output of buffer
12
. Preferably, buffer
12
has p- and n-channel transistors of sufficient drive strength to create a rather steep leading and trailing edges of the resulting clocking signal
22
, labeled as V
OUT
, produced from buffer
12
.
Typically, crystal
14
is connected to input/output pads of a chip
24
. Chip
24
is a single crystalline silicon substrate on which inverter
16
, buffer
12
, and electronic subsystem
20
can be formed. The oscillation frequency of a given crystal
14
is selected by the user and attached to the pins of chip
24
for driving a chosen frequency into buffer
12
, which then fashions the clocking signal that can drive a rather large sequentially operating subsystem
20
. Unfortunately, processing skews can sometimes change the voltage at which the p- and n-channel transistors of inverter
16
and buffer
12
transition from a relatively low output voltage to a relatively high output voltage. Those thresholds skews can be further compounded by temperature variations upon the chip
24
. These transistor threshold skews culminate in a variation in the overall threshold (or trigger) voltage of buffers
12
and
16
.
FIG. 2
illustrates the effects of threshold skew upon the resulting clock signal. For example, if the p- and n-channel transistors of buffer
12
are skewed due to transistor threshold skews, then the sinusoidal wave
18
will trigger a transition in buffer
12
at a different voltage. Alternatively, taking the trigger voltage as the point of reference, this could also be considered as an apparent DC shift in the sinusoidal waveform
18
. This is shown in phantom as waveform
18
a
and will produce an apparent DC offset voltage, labeled as V
OS
. If the thresholds of the p-channel transistor
26
and the n-channel transistor
28
of buffer
12
do not change relative to, or be adjusted to compensate for, this increased offset voltage of the sinusoid
18
a
, then the n-channel transistor
28
or p-channel transistor
26
may trigger much sooner or later, thereby causing an output waveform or clocking signal that has a greater mark or space timing.
In many instances, the incoming sinusoidal wave may be isolated from buffer
12
operation. In those instances, the incoming sinusoidal wave may not be accompanied by a DC offset, or a DC offset may be removed before placing the sinusoidal wave on the input of the buffer
12
. In these circumstances, a DC offset must be applied which is consistent with the threshold of buffer
12
. The mark/space ratio of the clocking signal
22
is then dependent primarily on any threshold voltage skews within p- and n-channel transistors
26
and
28
. For example, if the n-channel transistor
28
threshold is lowered relative to the p-channel transistor
26
, then n-channel transistor
28
will turn on much quicker as the input sinusoidal wave extends upward from a ground voltage towards to power supply rail. This will cause a skewing in the inverter
12
threshold and, thereby, a greater space-to-mark ratio (i.e., the low voltage value times will be greater than the high voltage value times). However, if the n-channel transistor
28
threshold increases relative to p-channel transistor
26
, then the overall threshold of inverter
12
will increase. In the example shown by waveform
22
in
FIG. 2
, an increase in the inverter threshold V
TH
, alternatively known as V
TRIG
, will cause the p-channel transistor
26
to turn on much sooner than the n-channel transistor
28
. This will skew the mark/space ratio so that the period of time for a mark will be greater than the period of time for a space. Thus, a duty cycle of the mark-to-space ratio will be greater than 50%. Even though the incoming sinusoidal signal (V
OSC
) does not carry an offset voltage, any skewing of the buffer
12
threshold value will cause a proportional skew in the duty cycle of the clocking signal
22
, shown as V
OUT
.
Most electronic subsystems rely upon a duty cycle that is approximately 50%. In other words, an electronic subsystem will expect an equal mark and space time for the clocking signal being used to synchronize the various circuits of an electronic subsystem or subsystems. Many microprocessor applications, for example, require a duty cycle of 50%+/−3% symmetry. If the duty cycle skews outside the acceptable tolerance range, either due to temperature variations or processing variations, then the desired application may be severely jeopardized or, worse yet, the application may fail.
It is, therefore, desirable that an improved clocking signal circuit be employed that can dynamically regulate the mark/space ratio even though processing and t
Conley & Rose, P.C.
Daffer Kevin L.
Mis David
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