System and method for representing a system level RTL design usi

Details System and method for representing a system level RTL design usi System and method for representing a system level RTL design usi

1997-10-23

2000-10-24

Lintz, Paul R.

G06F 1750

Patent

active

061356476

ABSTRACT:
A system and method for representing a system level RTL hardware design using an HDL independent RTL representation and translation into synthesizable RTL code. The present invention creates an object-oriented library which can be used to implement RTL hardware designs in terms of HDL independent objects. Instead of implementing multiple HDL instances of hardware modules, the invention enables software tool programmers to implement one HDL-independent instance of the hardware module. As a result, a programmer can focus his efforts on generating the functionality of the module and can be relieved from the time consuming task of generating the detailed syntax of multiple HDLs. The present invention also maintains synchronization across multiple HDLs so that a software designer can generate HDL code for any supported HDL, e.g., Verilog or VHDL, thus making software maintenance easier.

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