System and method for reducing the penalty associated with data

Details System and method for reducing the penalty associated with data System and method for reducing the penalty associated with data

1991-07-12

1995-03-07

Coleman, Eric

Boots, shoes, and leggings

3642434, 3642517, 364260, 364DIG1, 395425, G06F 1200

Patent

active

053966040

ABSTRACT:
A computer system having a central processor unit (CPU) with a reduced instruction set, a decoder and a data cache memory, for processing an instruction to retrieve data from a main memory to prevent a data cache miss. The system decodes an instruction requiring the CPU to load a value into a read only general purpose memory register, the instruction thereby indicating to the CPU to perform a prefetch operation and providing information corresponding to an address of the data to be fetched from the main memory. The system processes, substantially simultaneously, further instructions following the load register instruction and the prefetch operation by determining the address in main memory of the data to be prefetched using the information provided by the load instruction, fetching the data from the main memory, and storing the data in the data cache memory to permit accesses to the data and thereby reduce the penalty associated with a data cache miss.

REFERENCES:
patent: 5025366 (1991-06-01), Baror
patent: 5109524 (1992-04-01), Wagner
patent: 5146603 (1992-09-01), Frost
"CMOS PA-RISC Processor For a New Family of Workstations", by M. Forsyth et al., (IEEE COMPCOM Spring '91 Digest of Papers; Feb. 1991.
"System Design for a Low Cost PA-RISC Desktop Workstation", by R. Horning et al., (IEEE COMPCOM Spring '91 Digest of Papers; Feb. 1991.
"Architecture and Compiler Enhancements for PA-RISC Workstations", by D. Odnert et al., (IEEE COMPCOM Spring '91 Digest of Papers; Feb. 1991.

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