Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2002-02-14
2004-07-13
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S055000, C345S063000, C345S076000, C345S077000, C345S084000, C345S087000, C345S204000, C345S205000, C345S690000
Reexamination Certificate
active
06762739
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to electronic display drivers, and more particularly to a driver for a liquid crystal display capable of achieving a more rapid display response by reducing the intensity output rise time.
2. Description of the Background Art
FIG. 1
shows a single pixel cell
100
of a typical liquid crystal display. Pixel cell
100
includes a liquid crystal layer
102
, contained between a transparent common electrode
104
and pixel storage electrode
106
, a storage element
108
, and a switching transistor
110
. Storage element
108
is coupled at node
112
to pixel storage electrode
106
and, via switching transistor
110
, to a data input line
114
. Storage element
108
is also coupled, as is common electrode
104
to a common voltage supply terminal
116
(e.g., ground). Responsive to a select signal on select line
118
, which is coupled to the control terminal of switching transistor
110
, storage element
108
reads a data signal in from data line
114
, stores the signal, and asserts the signal on node
112
, even after the select signal is no longer present.
Liquid crystal layer
102
rotates the polarization of light passing through it, the degree of rotation depending on the root-mean-square (RMS) voltage across liquid crystal layer
102
. The ability to rotate the polarization is exploited to modulate the intensity of reflected light as follows. An incident light beam
120
is polarized by polarizer
122
. The polarized beam then passes through liquid crystal layer
102
, is reflected off of pixel electrode
106
, and passes again through liquid crystal layer
102
. During this double pass through liquid crystal layer
102
, the beam's polarization is rotated by an amount which depends on the data signal being asserted on pixel storage electrode
106
. The beam then passes through polarizer
124
, which passes only that portion of the beam having a specified polarity. Thus, the intensity of the reflected beam passing through polarizer
124
depends on the amount of polarization rotation induced in liquid crystal layer
102
, which in turn depends on the data signal being asserted on pixel storage electrode
106
.
Storage element
108
can be either an analog storage element (e.g. capacitative) or a digital storage element (e.g., SRAM latch). In the case of a digital storage element, a common way to drive pixel storage electrode
106
is via pulse-width-modulation (PWM). In PWM, different gray scale levels are represented by multi-bit words (i.e., binary numbers). The multi-bit words are converted to a series of pulses, whose time-averaged root-mean-square (RMS) voltage corresponds to the analog voltage necessary to attain the desired gray scale value.
For example, in a 4-bit PWM scheme, the frame time (time in which a gray scale value is written to every pixel) is divided into 15 time intervals. During each interval, a signal (high, e.g., 5V or low, e.g., 0V) is asserted on the pixel storage electrode
106
. There are, therefore, 16 (0-15) different gray scale values possible, depending on the number of “high” pulses asserted during the frame time. The assertion of 0 high pulses corresponds to a gray scale value of 0 (RMS 0V), whereas the assertion of 15 high pulses corresponds to a gray scale value of 16 (RMS 5V). Intermediate numbers of high pulses correspond to intermediate gray scale levels.
A particular signal being applied during a time interval is referred to as a “state”. For example, a high signal being asserted during one time interval is an “on” state. Similarly, a low signal being asserted during one time interval is referred to as an “off” state.
FIG. 2
shows a series of pulses corresponding to the 4-bit gray scale value (1010), where the most significant bit is the far left bit. The pulses are grouped to correspond to the bits of the binary gray scale value. Specifically, the first group B
3
includes 8 intervals (2
3
), and corresponds to the most significant bit of the value (1010). Similarly, group B
2
includes 4 intervals (2
2
) corresponding to the next most significant bit, group B
1
includes 2 intervals (2
1
) corresponding to the next most significant bit, and group B
0
includes 1 interval (2
0
) corresponding to the least significant bit. This grouping reduces the number of pulses required from 15 to 4, one for each bit of the binary gray scale value, with the width of each pulse corresponding to the significance of its associated bit. Thus, for the value (1010), the first pulse B
3
(8 intervals wide) is high, the second pulse B
2
(4 intervals wide) is low), the third pulse B
1
(2 intervals wide) is high, and the last pulse B
0
(1 interval wide) is low. This series of pulses results in an RMS voltage that is approximately ⅔ (10 of 15 intervals) of the full value (5V), or approximately 4.1V.
The resolution of the gray scale can be improved by adding additional bits to the binary gray scale value. For example, if 8 bits are used, the frame time is divided into 255 intervals, providing 256 possible gray scale values. In general, for (n) bits, the frame time is divided into (2
n
−1) intervals, yielding (2
n
) possible gray scale values.
Because the liquid crystal cells are susceptible to deterioration due to ionic migration resulting from a DC voltage being applied across them, the above described PWM scheme is modified to debias the cell. According to one method for debiasing the cells, the frame time is divided in half. During the first half, the PWM data is asserted on the pixel storage electrode, while the common electrode is held low. During the second half of the frame time, the complement of the PWM data is asserted on the pixel storage electrode, while the common electrode is held high. This results in a net DC component of 0V, avoiding deterioration of the liquid crystal cell, without changing the RMS voltage across the cell, as is well known to those skilled in the art.
FIG. 3
shows a response curve of an electrically controlled, birefringent liquid crystal cell. The vertical axis
302
indicates the percent of full brightness (i.e., maximum light reflection) of the cell, and the horizontal axis
304
indicates the RMS voltage across the cell. As shown, the minimum brightness (a dark pixel) is achieved at an RMS voltage Vtt. For some wavelengths of light, an RMS voltage less than Vtt results in a pixel that is not completely dark, as shown in FIG.
3
. For other wavelengths, all RMS voltages less than Vtt result in a dark pixel. In the portion of the curve between Vtt and Vsat, the percent brightness increases as the RMS voltage increases, until 100% full brightness is reached at Vsat. Once the RMS voltage exceeds Vsat, however, the percent brightness decreases as the RMS voltage increases.
FIG. 4
shows the response curve of a typical liquid crystal display as successive frames of a particular gray scale value are written to the cell. Each period of the wave form corresponds to the forward and reverse bias assertion of a single frame of data. Note that there is a delay from time t
0
, when the data is first asserted on the cell, until time t
1
, when the intensity output of the cell actually corresponds to the steady state RMS voltage of the grayscale value being asserted. The delay is referred to as the “rise time” of the cell, and results from the physical properties of the liquid crystals.
The cell rise time can cause undesirable visual artifacts on a display. The artifacts are most noticeable when the display is displaying an image of a light object moving across a dark background, or vice versa. In mild cases, the leading edge of the moving object may appear blurred, or the moving object may leave a ghost trail. In the case of small or rapidly moving objects, the object may disappear altogether. What is needed is a system and method for reducing the cell rise time in liquid crystal displays, thus reducing the visual artifacts resulting therefrom.
SUMMARY
A novel display driver circuit is described. The display driver overco
Aurora Systems, Inc.
Henneman & Saunders
Henneman, Jr. Larry E.
Kovalick Vincent E.
Shalwala Bipin
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