System and method for reducing shorting in memory cells

Details System and method for reducing shorting in memory cells System and method for reducing shorting in memory cells

2006-09-26

2006-09-26

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S238000, C438S624000, C365S173000, C257SE21660

Reexamination Certificate

active

07112454

ABSTRACT:
An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.

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