System and method for reducing processing errors during...

Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing

Reexamination Certificate

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Details

C700S121000, C700S225000, C235S462110, C235S462150, C235S462410, C250S492210, C438S007000, C438S016000

Reexamination Certificate

active

07953511

ABSTRACT:
A system and method is disclosed for reducing processing errors during the fabrication of integrated circuit wafers. A 2D dot matrix wafer scribe that contains coded information is placed on a wafer. The coded information contains wafer information such as the wafer lot number. The wafer is then placed in an ion implantation system. A camera in the ion implantation system is then used to photograph the dot matrix wafer scribe on the wafer. The information about the wafer is then decoded from the photograph of the dot matrix wafer scribe. A station controller that operates the ion implantation system then uses the information from the dot matrix wafer scribe to determine whether the wafer is suitable for ion implantation. The wafer is implanted only when the information from the dot matrix wafer scribe matches information about the wafer that has been previously stored in the station controller.

REFERENCES:
patent: 5350715 (1994-09-01), Lee
patent: 5841661 (1998-11-01), Buchanan et al.
patent: 6185511 (2001-02-01), Steffan et al.
patent: 6298280 (2001-10-01), Bonora et al.
patent: 6478532 (2002-11-01), Coady et al.
patent: 6596965 (2003-07-01), Jeong et al.
patent: 6597427 (2003-07-01), Katsu et al.
patent: 6729462 (2004-05-01), Babbs et al.
patent: 6748293 (2004-06-01), Larsen
patent: 6809809 (2004-10-01), Kinney et al.
patent: 6866200 (2005-03-01), Marx et al.
patent: 7023003 (2006-04-01), Li et al.
patent: 7034921 (2006-04-01), Tanaka
patent: 7041990 (2006-05-01), Kim et al.
patent: 7187993 (2007-03-01), Kay et al.
patent: 7229021 (2007-06-01), Vesikivi et al.
patent: 7266418 (2007-09-01), Nakayama et al.
patent: 7287698 (2007-10-01), Barrus
patent: 7314766 (2008-01-01), Sugamoto et al.
patent: 7346412 (2008-03-01), Tokorozuki et al.
patent: 7515982 (2009-04-01), Varadhan et al.
patent: 7652224 (2010-01-01), Lim
patent: 7680557 (2010-03-01), Kim et al.
patent: 7700381 (2010-04-01), Arikado et al.
patent: 7702413 (2010-04-01), Ushiku et al.
patent: 7813542 (2010-10-01), Lee et al.
patent: 7818652 (2010-10-01), Sakata
patent: 2007/0081714 (2007-04-01), Wallack et al.
patent: 2007/0142960 (2007-06-01), Bollinger et al.
patent: 2007/0152058 (2007-07-01), Yeakley et al.
patent: 2008/0037055 (2008-02-01), Yun
patent: 2008/0105748 (2008-05-01), Lei
patent: 2008/0313205 (2008-12-01), Elgar et al.

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