Coded data generation or conversion – Converter calibration or testing – Trimming control circuits
Reexamination Certificate
2007-06-09
2010-10-26
Barnie, Rexford N (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
Trimming control circuits
C341S161000
Reexamination Certificate
active
07821436
ABSTRACT:
A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.
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Bhowmik Prasenjit
Chakkirala Sumanth
Easwaran Prakash
Kali Bhattacharya Prasun
Khatri Mukesh
Barnie Rexford N
Cosmic Circuits Private Limited
Evergreen Valley Law Group P.C.
Lauture Joseph
Radhakrishnan Kanika
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