Electrical transmission or interconnection systems – Plural load circuit systems – Control of current or power
Reexamination Certificate
1999-08-24
2001-10-23
Ballato, Josie (Department: 2836)
Electrical transmission or interconnection systems
Plural load circuit systems
Control of current or power
C307S039000
Reexamination Certificate
active
06307281
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates in general to the field of electronic devices and more specifically to a system and method for reducing power dissipation in a circuit.
BACKGROUND OF THE INVENTION
Reducing power dissipation is an important concern in processor and circuit design. Increases in the density of microelectronic devices and the related need to minimize the heat generated by such devices provides one major impetus for such reduction. Reducing the amount of power dissipated at a microelectronic level can greatly reduce excess heat that may adversely impact both a product's performance and lifespan. The need to minimize power usage in mobile electronics and other battery-operated devices further provides impetus for reducing power dissipation. Additionally, the introduction of specialized circuitry to processors and other circuits prompts heightened concern about power dissipation. Such circuits, while providing improved performance and increased functionality, generally dissipate comparatively large amounts of power.
From the standpoint of processor or circuit design, a number of techniques have been used to reduce power usage. These techniques can be grouped into two basic strategies. First, the processor's circuitry is designed to use less power. Second, the processor is designed in a manner that permits power usage to be managed.
In the past, managing power usage has been primarily at the system level. Various “power down” and “sleep” modes have been implemented that permit large system components such as a disk drive, display, or the processor itself, to be intermittently powered down. Other application specific circuits or general processors have been introduced which similarly engage “stand by” modes wherein the majority of system level components in an application specific circuit or general processor are shut down while waiting for a real time interrupt or event. For example, a cellular phone may enter standby mode while waiting to receive an incoming call or message.
The entry of a device into a power down mode can be initiated in various ways, such as in response to a timer or in response to a processor instruction or real time interrupt. For example, a device may enter into a power down mode after it has been inactive for a preset period. Or, instruction-implemented power management may be developed to place power management under processor control. One such standard using instruction-implemented power management is the Advanced Power Management™ interface specification, developed jointly by Intel® and Microsoft®.
One approach to processor power management is described in U.S. Pat. No. 5,584,031, entitled “System and Method of Executing a Low Powered Delay Instruction.” In this approach, a special instruction specifies a number of timing cycles during which activity of a central processing unit is delayed.
Another approach to processor power management is described in U.S. Pat. No. 5,495,617, entitled “On Demand Powering of Necessary Portions of Execution Unit by Decoding Instruction Word Field Indications Which Unit is Required for Execution”. An instruction coder differentiates “control” instructions from “execute” instructions. If the instruction is a “control” instruction, it does not involve the execution unit and a standby signal can be sent to the execution unit.
These known systems and methods described above have limitations and disadvantages making them unsatisfactory alternatives for achieving reduced power dissipation in some circuits.
SUMMARY OF THE INVENTION
While the power management systems described above allocate control of power to a processor such that the powering down of a central processing unit or execution unit can be accomplished, neither of such systems provide the capability of reducing the power dissipated in individual elements of such central processing unit or execution unit. For example, a typical execution unit may include an arithmetic logic unit, an accumulator, a temporary register, a read controller, a micro-program address register, and other functional units used in execution. Neither U.S. Pat. No. 5,584,031 nor U.S. Pat. No. 5,495,617 provides for reducing the power dissipated by these individual elements in an execution unit or other system component.
Accordingly, a need has arisen for an improved system and method for reducing power dissipation in a circuit. The present invention provides a system and method for reducing power dissipation in a circuit that addresses shortcomings of prior systems and methods in addressing power dissipation in a circuit.
According to one embodiment of the invention, a method for selective allocation of power to elements of a circuit identifies at least one element of the circuit for reduced power dissipation and selects the at least one element. The method alters an input to the at least one element thereby reducing the power dissipated by the at least one element.
According to another embodiment of the invention, a system for the selective allocation of power to elements of a circuit comprises a logic component that is operable to identify at least one element of the circuit for reduced power dissipation. The system further comprises a selection signal generated by the logic component that is operable to select the identified at least one element and a control interface that is operable to reduce the power dissipated by the selected element in response to the selection signal.
In yet another embodiment of the present invention, a system for selectively reducing power dissipation in elements of a circuit comprises a logic component that is operable to identify at least one element of a circuit for reduced power dissipation, the logic component identifying the at least one element in response to analyzing instructions processed by an instruction handler. The system further comprises a selection signal generated by the logic component that is operable to select the identified at least one element and a control interface that is operable to alter an input to the identified at least one element in response to the selection signal and thereby cause the identified at least one element to enter a reduced power dissipation mode.
Various embodiments of the invention provide some or all of the following technical advantages. For example, power management is provided at an “on-chip” level as compared to a computer system level. The present invention also provides the advantage of applying power management to individual elements within a circuit. A further advantage of the present invention is the ability to reduce power dissipation in an element of a circuit without reducing the power supply of that element. A further advantage of the present invention is that an individual element within a processor or circuit can have its power supply turned off or significantly reduced without impacting the operation of the rest of the processor or circuit. Yet another advantage of the present invention is allowing more widespread use of specialized on-chip circuitry. For example, circuits for performing floating point operations, Fourier transforms and digital signal filtering can be included on-chip without incurring a significant increase in power dissipation during the operation of the circuit. Such specialized circuitry may function on reduced power or may be powered down except during time intervals when their functionality is required.
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Ballato Josie
Brady III W. James
Marshall, Jr. Robert D.
Polk Sharon
Telecky , Jr. Frederick J.
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