Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
1997-11-14
2001-09-11
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S214000, C345S087000, C345S090000, C345S098000
Reexamination Certificate
active
06288712
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to circuits for driving electronic displays, and more particularly to a system and method for using an internal sequencer to sequentially drive the select lines of a display.
2. Description of the Background Art
FIG. 1
shows a prior art display driver circuit
100
, for driving a display
102
which includes an array of pixel cells arranged in 768 rows and 1024 columns. Display driver circuit
100
includes select decoder
104
, row decoder
106
, write hold register
108
, pointer
110
, instruction decoder
112
, invert logic
114
, timing generator
116
, and input buffers
118
,
120
, and
122
. Driver circuit
100
receives clock signals via an SCLK terminal
124
, invert signals via an invert (INV) terminal
126
, data and addresses via a 32-bit system data bus
128
, and operating instructions via a 3-bit op-code bus
130
, all from a system (e.g., a computer) not shown. Timing generator
116
generates timing signals, by methods well known to those skilled in the art, and provides these timing signals to the components of driver circuit
100
via clock signal lines (not shown) to coordinate the operation of the various components.
Invert logic
114
receives the invert signals from the system via INV terminal
126
and buffer
118
, and receives the data and addresses from the system via system data bus
128
and buffer
120
. Responsive to a first invert signal ({overscore (INV)}), invert logic
114
asserts the received data and addresses on a 32-bit internal data bus
132
. Responsive to a second invert signal (INV), invert logic asserts the complement of the received data on internal data bus
132
. Internal data bus
132
provides the asserted data to write hold register
108
, and provides the asserted addresses to select decoder
104
, via 5 of the 32 lines, and to row decoder
106
, via 10 of the 32 lines.
Instruction decoder
112
receives opcode instructions from the system, via op-code bus
130
and buffer
122
, and, responsive to the received instructions, provides control signals, via an internal control bus
134
, to select decoder
104
, row decoder
106
, write hold register
108
, and pointer
110
. Responsive to the system asserting data on system data bus
128
and a first instruction (i.e., Data Write) on op-code bus
130
, instruction decoder
112
asserts control signals on control bus
134
, causing write hold register
108
to load the asserted data via internal data bus
132
into a first portion of write hold register
108
. Because internal data bus
132
is only 32 bits wide, 32 data write commands are necessary to load an entire line (1024 bits) of data into write hold register
108
. Pointer
110
provides an address, via a set of address lines
135
, to write hold register
108
, identifying the portion of write hold register
108
to which data is to be written. As each successive Data Write command is executed, pointer
110
increments the address asserted on lines
135
to identify the next 32-bit portion of write hold register
108
.
Responsive to the system asserting a row address on system data bus
128
and a second instruction (i.e., Load Row Address) on op-code bus
130
, instruction decoder
112
asserts control signals on control bus
134
causing row decoder
106
to store the asserted row address. Then, responsive to the system asserting a third instruction (i.e., Array Write) on op-code bus
130
, instruction decoder
112
asserts control signals on control bus
134
, causing write hold register
108
to assert the 1024 bits of stored data on a set of 1024 data output terminals
136
, and causing row decoder
106
to decode the stored row address and assert a write signal on one of 768 word-lines
138
corresponding to the decoded row address. The write signal on the corresponding word-line causes the data being asserted on data output terminals
136
to be latched into a corresponding row of pixel cells in display
102
.
Responsive to the system asserting a block address on system data bus
128
and a fourth instruction (i.e., Load Block Address) on op-code bus
130
, instruction decoder
112
asserts control signals on control bus
134
, causing select decoder
104
to store the asserted block address. Then, responsive to the system asserting a fifth instruction (i.e., Pixel Update) on op-code bus
130
, instruction decoder
112
asserts control signals on control bus
134
causing select decoder
104
to decode the asserted address and assert a block update signal on one of a group of 24 block select lines
140
corresponding to the decoded block address. The block update signal on the corresponding block select line causes all of the pixels cells of an associated block to assert the previously latched data onto their associated pixel electrodes (not shown in FIG.
1
).
FIG. 2
shows an exemplary dual-latch pixel cell
200
(
r,c,b
) of display
102
, where (
r
), (
c
), and (
b
) indicate the row, column, and block of the pixel cell, respectively. Pixel cell
200
includes a master latch
202
, a slave latch
204
, a pixel electrode
206
, and switching transistors
208
,
210
, and
212
. Master latch
202
is a static random access memory (SRAM) latch. One input of master latch
202
is coupled, via transistor
208
, to a Bit+data line
214
(
c
), and the other input of master latch
202
is coupled, via transistor
210
, to a Bit−data line
216
(
c
). The gate terminals of transistors
208
and
210
are coupled to word line
138
(
r
). The output of master latch
202
is coupled, via transistor
212
, to the input of slave latch
204
. The gate terminal of transistor
212
is coupled to block select line
140
(
b
). The output of slave latch
204
is coupled to pixel electrode
206
.
A write signal on word line
138
(
r
) places transistors
208
and
210
into a conducting state, causing the complementary data asserted on data lines
214
(
c
) and
216
(
c
) to be latched, such that the output of master latch
202
is at the same logic level as data line
214
(
c
). A block select signal on block select line
140
(
b
) places transistor
212
into a conducting state, and causes the data being asserted on the output of master latch
202
to be latched onto the output of slave latch
204
, and thus onto coupled pixel electrode
206
.
FIG. 3
illustrates how display
102
is divided into 24 blocks (0-23), each containing 32 rows, for purposes of updating the pixel cells. Each block contains 32 rows of pixel cells, all coupled to one block select line
140
(
b
). Accordingly, all of the pixel cells of a given block are updated simultaneously. The division of a display into blocks for the purpose of updating the pixel cells is further described in U.S. Pat. No. 5,278,652, which issued to Urbanus et al. on Jan. 11, 1994, and is incorporated herein by reference.
FIG. 4
shows the temporal relationship of the pixel updates. During the first SCLK cycle, a load address (LA) command loads the address of the first block to be updated (Block
0
). Then, during the next clock cycle, an update block command (UB) causes all of the pixel cells in Block
0
to be updated. This two-step sequence of loading an address and updating a block is repeated until each of the blocks in the display are updated.
FIG. 5
shows the temporal relationship of the row updates within a block. In particular, note that all rows within a block are updated simultaneously. For example, Rows
0
-
31
of Block
0
are all updated responsive to the first update block command. Similarly, Rows
0
-
31
of Block
1
are all updated responsive to the second update block command. This is because all of the pixels within a block are coupled to a common select line.
The above described prior art suffers a disadvantage, in that simultaneously updating all of the pixels within a block generates a relatively large amount of peak current. For example, for blocks having 32 rows of 1024 pixels, 32,768 pixel electrodes must be charged (or discharged) at one time. Furthermore
Campbell John Gray
Hudson Edwin Lyle
Pinkham Raymond
Worley, III W. Spencer
Aurora Systems, Inc.
Henneman & Saunders
Henneman, Jr. Larry E.
Nguyen Jimmy H.
Shalwala Bipin
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