Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-03-29
2003-06-03
Tran, M. (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S206000
Reexamination Certificate
active
06574127
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of integrated circuit design. Specifically, it relates to a system and method for reducing coupling and switching noise associated with datalines leading to and from an embedded memory, such as an embedded DRAM (eDRAM).
BACKGROUND OF THE INVENTION
Integrated circuit design of a microelectronic chip is generally aimed at reducing the size of components and connections/spacings between components, as well as increasing processing speed while maintaining the integrity of data signals. As technology develops, additional components are integrated on the chip resulting in an increased packing density for the microelectronic chip.
Typically, a high performance microprocessor chip uses a high-speed cache memory, for storing for example, instructions and data needed by a processor within the chip. The high-speed cache memory, referred to as the first level (L1) cache, is located proximate to the processor for maximizing efficiency and accuracy. Due to the size restriction of the cache, upon the occurrence of a data miss, the processor issues commands to get data from an off-chip main memory. A high data miss rate results in a significant performance penalty. To overcome the problem associated with data misses, a second level of cache memory (L2) is provided on the microprocessor chip for storing, for example, instructions and data needed by the processor.
The performance, such as in reliability and speed, of the cache memory is critical to the performance of the microprocessor chip. Cache memory is primarily made from static random access memory (SRAM) technology, such as a 6-transistor SRAM, which provides reliable performance. However, an SRAM cache memory is too large to integrate onto the microprocessor chip. SRAM also suffers alpha particle induced soft-error.
DRAM technology is typically four to ten times smaller than SRAM. However, conventional DRAM does not operate at speeds required for L2 cache memory. Technological developments have demonstrated an increase in the speed of DRAM with cycle times of 6 ns or less, thus making DRAM a suitable candidate for use in L2 cache memory.
A microprocessor chip, such as for a CPU, generally has a bandwidth of 64 to 256 bits. Embedded DRAM (eDRAM) providing the L2 cache of a microprocessor chip typically has a bandwidth of 256 bits for both incoming and outgoing buses. Accordingly, a typical eDRAM has 512 datalines.
The datalines must be packed physically as close as possible in order to fit onto the compact microprocessor chip and to occupy minimum space. In operation, the tightly packed datalines switch simultaneously, creating switching-associated noise and coupling noise that tends to affect the integrity of the data.
As technology develops wire widths (such as for datalines) and intervals are constantly being reduced for improving the packing density. A lower limit value is set to limit the thickness of the metal wire. Once the wire thickness is close to the lower limit value, the interval between the wire is reduced, while mutually opposing surface areas of wires are held constant. Thus, there is a tendency to increase capacitance between mutually neighboring wires causing an increase in coupling noise.
An illustration of a simplified layout of a portion of a prior art microprocessor chip is shown in FIG.
1
. The portion includes an L2 cache memory
10
coupled to a CPU block
20
. The CPU block
20
includes as an integer unit, a floating unit, a load store unit, L1 caches, etc., as known in the art.
Data retired by the CPU block
20
is stored temporarily in an incoming data register
80
of the CPU and is restored to the L2 cache
10
via outgoing datalines
60
. Datalines
60
are received by secondary sense amplifier block
30
of the L2 cache and are eventually written back to the L2 cache
10
.
Simultaneously, data stored in the L2 cache
10
are retrieved by the CPU block
20
through the secondary sense amplifier
30
via incoming datalines
50
. The retrieved data is stored temporarily in an incoming data register
70
of the CPU block
20
. Datalines
50
and
60
may be interleaved and are arranged in a compact space
40
.
As data is transmitted simultaneously over datalines
50
and
60
, coupling noise develops due to an up swing of adjacent dataline(s) as a dataline couples up adjacent dataline(s). Likewise, coupling noise develops due to a down swing of adjacent dataline(s) as a dataline couples down adjacent dataline(s). Furthermore, switching associated noise develops due to simultaneously switching a large number of electronic devices; such as data drivers, sense amplifiers, registers, buffers, etc. of the chip resulting in substrate and Vdd bouncing.
Several solutions exist for overcoming the switching-associated and coupling noise associated with the datalines of the L2 cache. One possible solution is to add a re-driver along the dataline to enhance the signal. A second possible solution is to add a coupling noise detector/eliminator device to minimize the coupling noise as disclosed in U.S. Pat. No. 6,097,209. These solutions require additional components which occupy additional space on the microprocessor chip. Hence, these solutions fail to reduce the size of the chip.
A third solution is to use differential signals for either or both outgoing and incoming datalines of the eDRAM. This causes a common rejection, thereby increasing dataline signal integrity. The use of differential signals has been applied to signal lines in which the signal lines are not as densely packed as the datalines of the microprocessor chip.
For example, in a DRAM array, bitline pairs carrying differential signals have been implemented using a bitline twist employing two metal levels in which one bitline of the pair is patterned on top of the other bitline of the pair. Coupling is canceled by providing alternating bitline pairs to have one twist point and remaining bitline pairs to have two twist points. Each bitline requires space laterally to accommodate the twist. The use of differential signals is not conducive for use in a very compact environment as is the case for the ingoing and outgoing datalines of the high-density, wide bandwidth eDRAM.
Accordingly, a need exists for a system and method for reducing noise due to congested datalines in an eDRAM.
SUMMARY
An aspect of the present invention is to provide a system and method for reducing noise due to congested datalines in an eDRAM.
Another aspect of the present invention is to provide a dataline wiring structural system using differential signals for use in a compact eDRAM environment.
Further, a not her aspect of the present invention is to provide a dataline wiring structural system for reducing coupling and switching associated noise without consuming additional space on a microelectronic chip.
Further still, another aspect of the present invention is to provide a dataline wiring structural system using differential signals for outgoing datalines only, for incoming datalines only, and outgoing and incoming datalines without consuming extra space on a microprocessor chip.
Accordingly, the present invention provides a dataline wiring structural system for an eDRAM on a micro-electronic chip that suppresses coupling and switching-associated noise associated with incoming and outgoing datalines by providing a plurality of metal levels upon which the datalines are positioned. At least one of the datalines carries a differential signal. The outgoing datalines are interleaved with the incoming datalines. Each of the differential datalines includes at least one vertical twist in which the true and complementary signal components of the differential signal change position from one metal level of the plurality of metal levels to another level.
In a first embodiment of the present invention, the datalines of the incoming or the outgoing datalines carry a differential signal, while the other of the incoming or outgoing datalines carries a single-ended signal. Two metal levels are provided, a first metal level and a second metal l
Hanson David R.
Hsu Louis L.
Joshi Rajiv V.
Dilworth & Barrese LLP
IBM Corporation
Tran M.
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