System and method for reducing lock time in a phase-locked loop

Oscillators – Phase shift type

Reexamination Certificate

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C327S158000, C327S161000

Reexamination Certificate

active

07969252

ABSTRACT:
Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop gains, delaying the feedback clock signal along the feedback path of a phase locked loop decreases lock time and prevents instability. A delay circuit may be used at any location along the feedback path of the phase locked loop.

REFERENCES:
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patent: 6320424 (2001-11-01), Kurd et al.
patent: 6359950 (2002-03-01), Gossmann et al.
patent: 6617932 (2003-09-01), Kushner et al.
patent: 6906565 (2005-06-01), Keaveney
patent: 6943600 (2005-09-01), Craninckx
patent: 7042260 (2006-05-01), Choi
patent: 7504893 (2009-03-01), Gonzalez et al.

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