System and method for reducing leakage in memory cells using...

Details System and method for reducing leakage in memory cells using... System and method for reducing leakage in memory cells using...

2005-09-06

2005-09-06

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S154000, C365S230060

Reexamination Certificate

active

06940778

ABSTRACT:
An embodiment of the invention provides a circuit for reducing power in memory cells. The input of the circuit is connected to the wordline of the memory cells. When the wordline is active, the output of the circuit applies a voltage near VDD to the positive voltage supply node of the memory cells. When the wordline is inactive, the output of the circuit applies a voltage that is reduced by at least one Vtfrom VDD to the positive voltage supply node of the memory cells.

REFERENCES:
patent: 4768166 (1988-08-01), Anami
patent: 5276652 (1994-01-01), Anami
patent: 6735143 (2004-05-01), Houston

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