System and method for reducing latency in a floating point proce

Details System and method for reducing latency in a floating point proce System and method for reducing latency in a floating point proce

1993-01-29

1995-02-14

Malzahn, David M.

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364748, G06F 750

Patent

active

053901347

ABSTRACT:
A rounding means is associated with a carry propagate adder of a floating point processor in order to reduce latency and enhance performance. The rounding mechanism performs a rounding function approximately simultaneously with an addition function performed by the carry propagate adder on fraction inputs FA, FB to ultimately derive a resultant fraction FR, thereby eliminating the need for a conventional post-normalize incrementer. The rounding mechanism has a carry select adder and rounding logic network. The rounding logic network communicates with the carry propagate adder and the carry select adder in order to provide rounding information to the carry select adder. The carry select adder and the rounding logic network jointly provide a rounded output, which is then normalized by the normalizer to thereby derive the resultant fraction.

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patent: 5241490 (1993-08-01), Poon
"IEEE Standard for Binary Floating-Point Arithmetic," Aug. 12, 1985, pp. 7-10.
J. T. Coonen, "An Implementation Guide to a Proposed Standard for Floating Point Arithmetic," IEEE Computer, pp. 68-78, Jan. 1980.
S. Waser & M. J. Flynn, "Introduction to Arithmetic for Digital Systems Designers," pp. 106-107, 123-124, 206-208, 1st Edition, 1982.

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