System and method for reducing ground bounce in integrated circu

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

3072468, 307451, 307263, H03K 1716

Patent

active

052143201

ABSTRACT:
A system and method for reducing the amount of ground bounce in output buffer circuits. The invention includes a first control circuit to control the amount of time it takes for a pull-up FET to be turned on, and thus the amount of time it takes for an output signal of the output buffer circuit to transition from a low to a high state. The invention also includes a second control circuit to control the amount of time it takes to turn on a pull down FET and thus the amount of time it takes for the output signal of the output buffer circuit to transition from a high to a low state. First and second control circuits each include an additional FET for controlling the amount of current supplied to the pull-up and pull-down FET, respectively. Each additional FET is driven by a voltage reference signal which is above the threshold of the additional FET. Thus, the additional FET is not fully on or off, but introduces a resistance into the control circuit, thus decreasing the amount of current supplied to the pull-up and pull-down FETs. Since the current amount of current provided to the final output FETs is reduced, their turn-on time is slower and thus the switching time of output buffer circuit is increased. As a result, the magnitude of ground bounce introduced by the output buffer circuit according to the present invention is significantly reduced.

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