System and method for recovering and deserializing a high...

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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C375S371000

Reexamination Certificate

active

07092466

ABSTRACT:
A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output bits corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bit stream jitter and intersymbol interference.

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patent: 5905769 (1999-05-01), Lee et al.
patent: 6959058 (2005-10-01), Yoo et al.
Digital Display Working Group, Digital Visual Interface DVI Revision 1.0, Apr. 2, 1999.

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