Electrical computers and digital processing systems: processing – Byte-word rearranging – bit-field insertion or extraction,...
Reexamination Certificate
2000-04-07
2003-09-09
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Byte-word rearranging, bit-field insertion or extraction,...
C712S224000, C708S209000
Reexamination Certificate
active
06618804
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the field of digital computers and more specifically to functional units for processing predetermined types of instructions. The invention particularly provides a circuit or functional unit for use in connection with execution of an instruction for rearranging bits of a data word in accordance with a mask.
BACKGROUND OF THE INVENTION
Computers process data in accordance with instructions. One type of instruction which has been proposed is a so-called “sheep and goats” instruction which accepts as operands a data word and a mask word and rearranges the bits of the data word in accordance with the mask word. In the rearranged data word, the bits of the data word in bit positions which correspond to bits of the mask which are clear, or have the value “zero,” are shifted to the “left” end of the rearranged data word with their order being preserved, and the bits of the data word in bit positions which correspond to bits of the mask which are set, or have the value “one,” are shifted to the right end of the data word with their order being preserved. For example, if an eight bit data word has the value “abcdefgh” (where the letters represent binary integers having the value “one” or “zero”), and the mask word corresponds to “10011011,” in the rearranged data word generated when the “sheep and goats” instruction is executed with these as operands, the bits “b,” “c,” and “f,” all of which are in bit positions for which the mask bits are clear would be shifted to the left, preserving their order “bcf,” and the bits “a,” “d,” “e,” “g,” and “h,” all of which are in bit positions for which the mask bits are set would be shifted to the right, preserving their order “adegh,” with the result being the rearranged data word “bcfadegh.” Essentially, the “sheep and goats” instruction results in a rearrangement of bits of a data word into two groups as defined by bits of a mask word, one group (the “sheep”) corresponding to those bits for which the bits of the mask word are clear, and the other (the “goats”) corresponding to those bits for which the bits of the mask word are set, and in addition preserves order in each group.
In a variant of the “sheep and goats” instruction, the bits of the rearranged data word in bit positions for which the bits of the mask are either set or clear (but preferably not both) will be set to a predetermined value. Generally, it has been proposed, for example, that the bits of the rearranged data word in bit positions for which the bits of the mask are clear will be set to zero, but the variant may be used with either the “sheep” or the “goats,” and the predetermined value may be either “one” or “zero.”
A “sheep and goats” instruction can find utility in connection with, for example, performing various bit permutations, for example, using a mask consisting of alternating set and clear bits will result in a so-called “unshuffle” permutation of a data word. In addition, the variant can be useful in connection with using a set of originally discontiguous bits to perform a multi-way dispatch, or jump, by making the bits contiguous and using the result to form an index into a jump table.
SUMMARY OF THE INVENTION
The invention provides a new and improved circuit or functional unit for use in connection with execution of an instruction for rearranging bits of a data word in accordance with a mask.
In brief summary, the invention provides a system for rearranging data units of a data word in accordance with a mask word, the mask word having a plurality of mask bits each associated with a data unit, each mask bit having one of a set condition and a clear condition. The system includes an array of interconnected swap modules organized in a series of swap stages, each swap module having two inputs and two outputs. Each swap module is configured to receive at each input a data unit and associated mask bits and couple the data units to the respective outputs in relation to the associated mask bit's condition.
REFERENCES:
patent: 4583199 (1986-04-01), Boothroyd et al.
patent: RE33664 (1991-08-01), Kang et al.
patent: 5487159 (1996-01-01), Byers et al.
patent: 5682340 (1997-10-01), Arends et al.
patent: 5696922 (1997-12-01), Fromm
patent: 5777906 (1998-07-01), Lau et al.
patent: 6098087 (2000-08-01), Lemay
Knuth, Donald E. The Art of Computer Programming, vol. 3: Sorting and Searching, second edition. Addison-Wesley, Reading, Massachusetts, 1998. Section 5.3.4: Networks for Sorting (pp. 219-247).
Lawrence Peter
Steele, Jr. Guy L.
Cesari and McKenna LLP
Sun Microsystems Inc.
Tsai Henry W. H.
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