Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2005-09-13
2005-09-13
Ho, Duc (Department: 2665)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S392000, C370S466000, C370S474000
Reexamination Certificate
active
06944168
ABSTRACT:
A system and method for facilitating packet transformation of multi-protocol, multi-flow, streaming data. Packet portions subject to change are temporarily stored, and acted upon through processing of protocol-dependent instructions, resulting in a protocol-dependent modification of the temporarily stored packet information. Validity tags are associated with different segments of the temporarily-stored packet, where the state of each tag determines whether its corresponding packet segment will form part of the resulting modified packet. Only those packet segments identified as being part of the resulting modified packet are reassembled prior to dispatch of the packet.
REFERENCES:
patent: 5541920 (1996-07-01), Angle et al.
patent: 5566170 (1996-10-01), Bakke et al.
patent: 5598410 (1997-01-01), Stone
patent: 5600598 (1997-02-01), Skjaveland et al.
patent: 5666353 (1997-09-01), Klausmeier et al.
patent: 5764641 (1998-06-01), Lin
patent: 5812476 (1998-09-01), Segawa
patent: 5828654 (1998-10-01), Takase et al.
patent: 5896383 (1999-04-01), Wakeland
patent: 5901095 (1999-05-01), Crafts
patent: 5907511 (1999-05-01), Crafts
patent: 5923596 (1999-07-01), Wu et al.
patent: 5943481 (1999-08-01), Wakeland
patent: 5973952 (1999-10-01), Crafts
patent: 5995439 (1999-11-01), Watanabe et al.
patent: 6021132 (2000-02-01), Muller et al.
patent: 6032190 (2000-02-01), Bremer et al.
patent: 6046979 (2000-04-01), Bauman
patent: 6046980 (2000-04-01), Packer
patent: 6047002 (2000-04-01), Hartmann et al.
patent: 6072989 (2000-06-01), Witters et al.
patent: 6136638 (2000-10-01), Lee et al.
patent: 6141686 (2000-10-01), Jackowski et al.
patent: 6166403 (2000-12-01), Castagnetti et al.
patent: 6167445 (2000-12-01), Gai et al.
patent: 6175568 (2001-01-01), Awdeh
patent: 6185635 (2001-02-01), O'Loughlin et al.
patent: 6449656 (2002-09-01), Elzur et al.
patent: 6606317 (2003-08-01), Beadle et al.
patent: 2003/0046429 (2003-03-01), Sonksen
“Frame Based ATM over SONET/SDH Transport (FAST),” The ATM Forum, Technical Committee, fb-fbatm-0151.000, Jul. 2000, 37 pgs.
William Wong, “Network Processors Take The High Road . . . And The Low Road,” Electronic Design, Jul. 10, 2000, http://www.planetee.com/planetee/servlet/DisplayDocument?ArticleID=6798, Retrieved Jun. 15, 2001, 3 pgs.
“Network Processors Take The High Road . . . And The Low Road,” Electronic Design, Jul. 10, 2000, http://www.planetee.com/planetee/servlet/DisplayDocument?ArticleID=6799, Retrieved Jun. 15, 2001, 2 pgs.
“Network Processors Take The High Road . . . And The Low Road,” Electronic Design—Jul. 10, 2000, http://www.planetee.com/planetee/servlet/DisplayDocument?ArticleID=6800, Retrieved Mar. 7, 2002, 3 pgs.
“Network Processors Take The High Road . . . And The Low Road,” Electronic Design, Jul. 10, 2000, http://www.planetee.com/planetee/servlet/DisplayDocument?ArticleID=6802, Retrieved Jun. 15, 2001, 1 pg.
“Network Processors Take The High Road . . . And The Low Road,” Electronic Design, Jul. 10, 2000, http://www.planetee.com/planetee/servlet/DisplayDocument?ArticleID=6804, Retrieved Jun. 15, 2001, 1 pg.
“Network Processors Take The High Road . . . And The Low Road,” Electronic Design, Jul. 10, 2000, http://www.planetee.com/planetee/servlet/DisplayDocument?ArticleID=6806, Retrieved Jun. 15, 2001, 1 pg.
“Network Processors Take The High Road . . . And The Low Road,” Electronic Design, Jul. 10, 2000, http://www.planetee.com/planetee/servlet/DisplayDocument?ArticleID=6808, Retrieved Jun. 15, 2001, 1 pg.
“EZchip Technologies Completes Filing Patent Applications For Its 10/40G Network Processor Core Technology,” http://www.ezchip.com/html/press_000918.html, printed Jan. 22, 2001, 3 pgs.
“7-Layer Packet Processing: A Performance Analysis, White Paper,” EZchip, http://www.ezchip.com/html/tech_7layers.html, Retrieved Jan. 22, 2001, 8 pgs.
“Network Process Designs for Next-Generation Networking Equipment, White Paper,” EZchip, http://www.ezchip.com/html/tech_nsppaper.html, Retrieved Jan. 22, 2001, 8 pgs.
“Gilder Technology Report,” EZchip, Sep. 2000, http://www.ezchip.com/html/gilder.html, Retrieved Jan. 22, 2001, 2 pgs.
“Putting Routing Tables in Silicon,” IEEE Network, vol. 6, No. 1, Jan. 1992, 11 pgs.
Bossardt et al., “ABR Architecture and Simulation for an Input-Buffered and Per-VC-Queued ATM Switch,” Department of Electrical and Computer Engineering, University of Illinois, 6 pgs.
“C-5™ Digital Communications Processor,” C-PORT, A Motorola Company, Product Brief, Date Unknown, 8 pgs.
David Husak, “Network Processors: A Definition and Comparison,” C-PORT, A Motorola Company, May 3, 2000, 9 pgs.
“Products,” Applications, C-PORT, A Motorola Company, http://www.cportcorp.com/products/applications.htm, Retrieved Jan. 23, 2001, 3 pgs.
Husak et al., “Network Processor Programming Models: The Key to Achieving Faster Time-to-Market and Extending Product Life,” C-PORT, A Motorola Company, May 4, 2000, 8 pgs.
Paatela Jeremy B.
Sarkinen Scott A.
Trivedi Hemant Vrajlal
Ho Duc
Patterson Thuente Skaar & Christensen P.A.
SLT Logic LLC
LandOfFree
System and method for providing transformation of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for providing transformation of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for providing transformation of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3433646