Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural oscillators controlled
Reexamination Certificate
1999-05-19
2001-02-27
Grimm, Siegfried H. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural oscillators controlled
C331S014000, C331S017000, C331S025000, C331S049000, C331S055000, C327S292000
Reexamination Certificate
active
06194969
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to timing in electronic systems, and, more particularly, to systems employing master and slave clocks that are phase-aligned.
DESCRIPTION OF THE RELATED ART
The need to generate a local signal which is synchronized with an external reference signal is critical in many electronics applications such as frequency synthesis, clock recovery, clock generation and frequency demodulation. This coherence between the reference signal and the local replica is referred to as “phase synchronization”. This implies either that local signal is typically either in phase with the external reference signal or is offset from the reference signal by some phase constant.
At the heart of many such synchronization circuits is some form of a phase locked loop (PLL). Phase-locked loops are feedback control loops, whose controlled parameter is the phase of a locally generated replica of an incoming reference signal. Phase-locked loops have three basic components: a phase detector, a loop filter, and a voltage-controlled oscillator.
Generally speaking, electronic systems such as computer systems produce a master clocking signal from a crystal. The master clocking signal may be fed into a PLL to produce many identical clock signals (e.g. fanout) that are used to synchronize the components of the computer system.
The master clock signal is a critical component of the computer system. The failure of the master clock signal may disable the entire system. Thus, to alleviate this problem, some systems incorporate clock sources to generate two master clock signals, one of which is redundant. Upon a failure of the first master clock signal, the system is shut down and may be reinitialized using the second master clock signal. However, such a requirement disrupts system operation. Accordingly, it would be desirable to provide a system that is operable to fail-over from one clock source to another clock source without having to reinitialize the system.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a system and method for providing master and slave phase-aligned clocks. Upon a failure of a master clock signal, the system switches over to a slave clock signal in phase alignment with the master clock signal. In one embodiment, the master clock signal is from a first clock source, while the slave clock signal is from a second clock source. The second clock source comprises a phase locked loop (PLL) including a switch, which is coupled to selectively provide the control signal to a voltage controlled oscillator (VCO). The switch may also provide a reference control voltage to the VCO. This configuration may advantageously allow a phase-aligned slave clock to replace a master clock upon failure of the master clock.
In a further embodiment, the first clock source is comprised on a first clock board, and the second clock source is comprised on a second clock board. In one embodiment, the first clock board is different from the second clock board. In another embodiment, the first clock board is configured as a hot-swappable clock board. The first clock board may be removed from the system, such as upon a failure, and a third clock board placed in the system in place of the first clock board. The second clock board is switched from being the slave clock source to the master clock source. The third clock board is configured to operate as the slave clock source upon being placed in the system. The hot-swappable clock board may advantageously result in higher uptime for the system as a failed clock board may be replaced while the system is in use.
A method is likewise contemplated for providing redundant clock signals. The method comprises, in one embodiment, providing a first clock signal as a master clock signal. The method further provides a second clock signal as a slave clock signal, with the slave clock signal phase aligned with the master clock signal. Upon a failure of either the master clock signal or the slave clock signal, the method notifies a user of the failure. Upon the failure of the first clock signal, the method switches the second clock signal in place of the first clock signal as the master clock signal. In another embodiment, the method further comprises replacing the first clock signal with a third clock signal as the slave clock signal. In this embodiment, the third clock signal is phase aligned with the second clock signal. The method may advantageously maintain a continuous clock in the system while switching between clock sources.
In preferred embodiments, clock switching from a failed master clock source to a redundant slave clock source is automatic and does not substantially interrupt or interfere with the propagation of the master clock signal or other operations of the system. No halt and restart are necessary. The clock change is transparent to any local clock loads using the master clock signal as the local clock signal.
REFERENCES:
patent: 4025874 (1977-05-01), Abbey
patent: 4282493 (1981-08-01), Moreau
patent: 5648964 (1997-07-01), Inagaki et al.
patent: 5969558 (1999-10-01), Abe
Motorola, Inc., Semconductor Technical Data, “Dynamic Switch PLL Clock Driver,” Sep. 1997, pp. 1-6.
Conley Rose & Tayon PC
Grimm Siegfried H.
Kivlin B. Noäl
Sun Microsystems Inc.
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