Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
2004-02-04
2010-06-15
Shah, Kamini S (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
C702S057000, C702S058000, C702S079000, C702S089000, C702S125000, C703S003000, C703S004000, C703S013000, C703S014000, C714S055000, C714S814000, C714S815000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07739098
ABSTRACT:
Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.
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Clerkin Brian
Hollands Steve
Küçükçakar Kayhan
Mize Loa
Seigel Andrew J.
Bever Hoffman & Harms LLP
Harms Jeanette S.
Patel Shambhavi
Shah Kamini S
Synopsys Inc.
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