System and method for providing a low jitter data receiver...

Details System and method for providing a low jitter data receiver... System and method for providing a low jitter data receiver...

2007-06-19

2007-06-19

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S076000, C327S096000, C327S097000

Reexamination Certificate

active

10973743

ABSTRACT:
A system and method is disclosed for providing a clock and data recovery circuit that comprises a low jitter data receiver. The low jitter data receiver comprises a phase interpolator, an amplifier unit and a data sampling comparator. The phase interpolator and the amplifier unit provide the data sampling comparator with a single ended clock signal that is relatively immune to power supply noise. The data sampling comparator samples an input data stream with minimal jitter due to power supply noise. The data sampling comparator consumes less static power than a current mode logic D flip flop and also has output levels that are compatible with complementary metal oxide semiconductor (CMOS) logic.

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