Static information storage and retrieval – Floating gate
Reexamination Certificate
2006-03-27
2008-11-04
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Floating gate
C365S185180, C365S185050, C257S315000
Reexamination Certificate
active
07447064
ABSTRACT:
A system and method is disclosed for providing a CMOS compatible single poly electrically erasable programmable read only memory (EEPROM) with memory cells that comprise an NMOS program transistor. In a first embodiment the memory cells of the EEPROM comprise a PMOS control capacitor. In a second embodiment the memory cells of the EEPROM comprise an NMOS control capacitor. A well bias voltage is applied to the NMOS program transistor instead of a gate bias voltage. The well bias voltage enables the injection of (1) channel hot electrons, (2) second hot electrons initiated by the channel hot electrons, and (3) drain impact ionization hot electrons into a floating gate of the NMOS program transistor.
REFERENCES:
patent: 6853583 (2005-02-01), Diorio et al.
patent: 6950342 (2005-09-01), Lindhorst et al.
patent: 2007/0097743 (2007-05-01), Fang et al.
Nader Akil et al., “Optimization of Embedded Compact Nonvolatile Memories for Sub-100-nm CMOS Generations”, IEEE Transactions on Electron Devices, vol. 52, No. 4, Apr. 2005, pp. 492-499.
A. Hoefler et al., “Statistical Modeling of the Program/Erase Cycling Acceleration of Low Temperature Data Retention in Floating Gate Nonvolatile Memories”, IEEE 40th Annual International Reliability Physics Symposium, Dallas, Texas, 2002, pp. 21-25.
Margaret L. French et al., “Design and Scaling of a SONOS Multidielectric Device for Nonvolatile Memory Applications”, IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part A, vol. 17, No. 3, Sep. 1994, pp. 390-397.
Yang (Larr) Yang et al., “Charge Retention of Scaled SONOS Nonvolatile Memory Devices at Elevated Temperatures”, Solid-Sate Electronics 44 (2000), pp. 949-958.
L. Chang et al., “Non-Volatile Memory Device with True CMOS Compatibility”, Electronics Letters, vol. 35, No. 17, Aug. 19, 1999, pp. 1443-1445.
Bu Jiankang
Jacobson Lee
Parker David Courtney
Hoang Huan
National Semiconductor Corporation
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