Oscillators – Electromechanical resonator – Crystal
Reexamination Certificate
2002-05-14
2004-03-09
Kinkead, Arnold (Department: 2817)
Oscillators
Electromechanical resonator
Crystal
C331S066000, C331S176000, C331S1160FE, C331S069000, C331S068000
Reexamination Certificate
active
06703906
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of programmable oscillators, and more particularly to systems and methods including high accuracy EPROM programmable phase locked loop oscillators.
BACKGROUND OF THE INVENTION
The CY2037 from Cypress Semiconductor Corporation (San Jose, Calif.), is an EPROM-programmable (electrically programmable read only memory), high-accuracy and resolution, PLL-based (phase-locked loop) digitally controlled crystal oscillator (DCXO). The device has a low jitter specification, e.g., <±100 ps (pk—pk) at 5V and f>33 MHz and <±125 ps (pk—pk) at 3.3V and f>33 MHz. The device is available die form, i.e., without packaging, and attaches directly to a 10-30 MHz crystal. The oscillator device may be packaged into various through-hole or surface mount packages. A block diagram of this circuit is shown in FIG.
1
A.
Traditionally, an oscillator crystal is calibrated in an operation termed the “final plate”, from an initial accuracy of within 2,000-3,000 ppm from the nominal frequency desired to within 10-25 ppm (typical) from the nominal desired frequency. This is a significant mechanical step, and constitutes the final calibration of the oscillator after it is mounted in a module. The final plate involves selectively depositing a film or plating of metal on a prepared pre-plate portion of the surface of the crystal, to mechanically alter the resonant frequency of the crystal. This process is typically manually assisted, requiring a skilled technician to carefully apply the plating to adjust the operating frequency of the crystal. Not only the thickness, but also the placement of the plating is critical; if it is not exactly concentric over the pre-plate region, phase noise and jitter are increased. In fact, as a rule, phase noise and jitter increase after the final plate. The final plate process also results in loss of yield. For example, there is a probability of plating adhesion failure. Further, the final plate process is performed with the crystal exposed, and thus more sensitive to environmental influences. After the crystal is tuned by the final plate, the crystal is sealed. Thus, the final plate process is expensive, labor consuming, reduces crystal quality, and potentially induces defects.
Precision crystal oscillators (PXO) such as the Micro Analog Systems (Espoo, Finland) MAS9271 and MAS1173, which include a digitally controlled capacitive tuning network for trimming a crystal frequency, are typically calibrated and operated independently of a digital frequency synthesizer. Thus, using a PXO, a crystal is tuned to a desired frequency, to within a small tolerance. This may include a final plate process. The digital frequency synthesizer is then programmed using the nominal multiply and divide values to achieve the desired output frequency.
In principle, the oscillator devices can be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping from an oscillator manufacturer. This would enable fast-turn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals or inventory of customized assemblies. In this case, the oscillators are not field programmable, and an integrator of oscillators into products must still specifically order a particular oscillator at a predefined frequency, and must still await the customization by the oscillator manufacturer and incur potential set-up charges, which may be significant for small orders, as well as the added cycle time of days or weeks.
The CY2037 contains an on-chip oscillator and a separate oscillator tuning circuit for fine-tuning of the output frequency. The crystal capacitive load can be selectively adjusted by programming a set of seven EPROM bits. This feature is typically used to compensate for crystal variations or to obtain a more accurate synthesized frequency.
The typical use of a programmable oscillator starts with an oscillator crystal trimmed to a nominal value. Then, the oscillator circuit is permanently programmed (in EPROM) with the multiply and divide ratios. Finally, at least in the case of the CY2037, the operating frequency of the crystal is tuned with the tuning bits to achieve a desired maximum error.
The CY2037 PLL die has a very high resolution. It has a 12-bit feedback counter multiplier and a 10-bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with low error, for example zero or low parts per million (ppm) The clock can be further modified by eight output divider options of 1, 2, 4, 8, 16, 32, 64 and 128. The divider input can be selected as either the PLL or crystal oscillator output, providing a total of sixteen separate output options. The output is selectable between TTL and CMOS duty cycle levels.
The nominal output frequency of the PLL is determined by the following formula:
F
PLL
=2×(
P+
5)/(
Q
+2)×
F
REF
where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values.
One version of the CY2037 contains a special tuning circuit to fine-tune the output frequency of the device. The tuning circuit consists of an array of eleven logarithmically sized load capacitors on both sides of the oscillator drive inverter. The capacitor load values are EPROM programmable with seven Osc_Tune bits, and can be increased in small increments. As the capacitor load is increased the circuit is fine-tuned to a lower frequency. The capacitor load values vary from 0.17 pF to 8 pF for an approximate 100:1 total control ratio.
The CY2037 uses EPROM programming with a simple 2-wire, 4-pin interface that includes VSS and VDD. Clock outputs can be generated up to 250 MHz. According to the design, the entire configuration of the EPROM can be reprogrammed one time, allowing programmed inventory to be altered or reused. The CY2037 includes a 44 bit by 2 row EPROM block, which holds all of the configuration information. The programming word contains the data from the EPROM and a row select (RowSel) bit, which determines the row being accessed during normal operation. Cypress advises that the bit should match in both rows, and therefore, when row 0 is programmed, row 1 is otherwise left unprogrammed, with the RowSel bit row 0 programmed to 0. When row 1 is programmed, the RowSel bit of row 0 is programmed to 1, a permissible overwrite.
The CY2037 contains a shadow register in addition to the EPROM register, which is optionally disabled. The shadow register is an exact copy of the EPROM register and is the default register when the Valid bit is not set. It is useful when the prototype or production environment calls for measuring and adjusting the CLKOUT frequency multiple times. Multiple adjustments can be performed with the shadow register. Once the desired frequency is achieved, the EPROM register is permanently programmed.
Accordingly, the following essential features of the CY2037 are controlled based on data stored in the EPROM; Feedback counter value (P); Reference counter value (Q); Output divider selection; Oscillator Tuning (load capacitance values); Duty cycle levels (TTL or CMOS); Power management mode (OE or PWR_DWN); Power management timing (synchronous or asynchronous); and Output Source Frequency (PLL or Crystal).
A PLL-based frequency synthesizer uses a reference input to generate output clocks. The reference can be provided by a quartz crystal or an external clock source. The accuracy and stability of the output clocks in a PLL-based frequency synthesizer are directly proportional to those of the reference. Thus, it is important to provide a stable, accurate, and appropriate reference input.
Jitter is an effect caused by an irregularity in the crystal oscillation and/or logic transitions of the circuit electronics. This can be caused by rapid changes in power supply voltage, logic transition voltage, stochastic processes, radio frequency interferences, or the like.
FIG. 1
shows the block diagram of a CY2037 PLL-bas
Cardinal Components, Inc.
Kinkead Arnold
Milde & Hoffberg LLP
LandOfFree
System and method for programming oscillators does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for programming oscillators, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for programming oscillators will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3236914