Boots – shoes – and leggings
Patent
1993-10-27
1996-02-20
Teska, Kevin J.
Boots, shoes, and leggings
364489, 364490, 364491, H01L 2500
Patent
active
054935040
ABSTRACT:
A design system of a logic circuit including a logic synthesis and processing unit and a set data processing unit. The set data processing unit includes a node table which records elements of a set. A control unit of the logic synthesis and processing unit reads set data from the node table, assigns a binary number to each element, and transfers them to a control unit of the set data processing unit. The control unit of the set data processing unit separates the set data in accordance with 0 and 1 of individual digits of the binary numbers, generates a 0-suppressed binary decision diagrams of a logic function, and stores them to the node table. In generating the 0-suppressed binary decision diagram, node sharing and 0-suppress node elimination are applied. The 0-suppress node elimination is applied to each intermediate node having edges e0 and e1, which are associated with 0 and 1 of each position of digits. When the edge e1 of an intermediate node points to a 0-terminal node, the intermediate node, the edge e1, and the 0-terminal node are eliminated, and an edge pointing the intermediate node is directly connected to e0 of the intermediate node. The 0-suppressed binary decision diagram is formed in the node table. A subset whose element number is considerably smaller than that of the entire set can be represented by a graph which includes a smaller number of nodes than a conventional binary decision diagram.
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Nippon Telegraph and Telephone Corporation
Teska Kevin J.
Walder, Jr. Stephen J.
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