Data processing: artificial intelligence – Knowledge processing system
Reexamination Certificate
1999-12-14
2003-06-24
Starks, Jr., Wilbert L. (Department: 2121)
Data processing: artificial intelligence
Knowledge processing system
C706S046000, C706S052000
Reexamination Certificate
active
06584455
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and method for identifying design errors in integrated circuits, and in particular to a system and method for using a trainable probabilistic model to predict, detect, and recover from design errors in an integrated circuit design and verification process. This invention relates specifically to design error prediction, while the related divisional patent applications referenced above relate to design error detection and design error recovery, respectively.
2. Related Art
Integrated circuits are becoming increasingly complex as the sizes of transistors and circuit traces continue to decrease, thereby allowing the construction of greater numbers of transistors and logic elements in smaller and smaller packages. As the complexity of integrated circuits, such as, for example, microprocessors, microcontrollers, analog-to-digital converters, and digital signal processors, has increased, the time typically allotted from initial design to final production has steadily decreased due to factors such as market demand, competition, and semiconductor manufacturing improvements.
Consequently, the design of sub-components of integrated circuits are often completed in parallel by multiple teams of designers using a variety of design tools. As a result, it is possible for design errors to be introduced into an integrated circuit that may go undetected until late in the design process, or possibly not even until after release of a production circuit. Further, the cost of corrective action in addressing design errors typically increases dramatically as circuit design nears completion, and may be most expensive following completion of design and production.
The problem of integrated circuit design error detection has been addressed in several ways. For example, one technique uses a probability network to analyze circuit performance after completion of circuit design to detect manufacturing errors in emitter and base resistors in a VLSI circuit. However, this technique does not apply to other stages or steps of the VLSI circuit design. Further, other types of logic errors are not addressed by this technique.
In another approach, a fault-simulation based technique is used to identify erroneous signals in a VLSI circuit by that can be corrected by re-synthesis of the erroneous signals. The fault-simulation of this technique generates erroneous vectors by random simulation. The erroneous vectors are binary or three valued input vectors that can be used to differentiate between a signal as implemented in a VLSI circuit, and the signal as specified in the circuit design. The correcting power of a particular signal is measured in terms of the signal s correctable set, namely, the maximum set of erroneous input vectors that can be corrected by re-synthesizing the signal. Only the signals that can correct every erroneous input vector are considered as a potential error source. This technique deals with circuit level signal errors, and not design errors, or errors introduced by design tools or methods of design.
In a similar approach, a fault-simulation based technique is used to identify erroneous signals in a sequential VLSI circuit by that can be corrected by re-synthesis of the erroneous signals. This technique locates an erroneous signal in a specific class of logic design errors, and provides a methodology to test whether an incorrect signal can be fixed by re-synthesizing the signal. In other words, this technique provides a method for correcting an erroneous output of a circuit without addressing the root cause of the error. However, re-synthesis of an erroneous signal requires the addition of additional transistors and logic elements to a particular portion of an integrated circuit that is affected by the erroneous signal. Consequently, while re-synthesis of an erroneous signal may fix a specific problem in a circuit, such a fix may introduce other design errors as well as timing and power problems elsewhere in the circuit as a result of the additional transistors and logic elements.
Another technique uses behavioral simulation models to analyze the dependability of a logic circuit early in the design of the circuit. This technique requires that a circuit design be abstracted into a number of discrete levels. The technique then uses the discrete levels to create a behavioral simulation model for performing circuit functional verification, circuit performance evaluation, and circuit dependability analysis. However, because this technique uses a single model, circuit design errors not covered by the model go undetected. Further, where error symptoms are found, there is no mechanism for backtracking to the source of the errors. Finally, this technique is applicable only at early stages of the design.
Still another technique uses a diagnostic algorithm based on backward-propagation techniques to localize design errors in combinational logic circuits. This technique addresses single logic gate replacement and insertion errors. In other words, this technique assumes the existence of a single gate error as the root cause of an error in a logic circuit.
Therefore, what is needed is a system and method for reliably detecting integrated circuit design errors as early in the design process as possible while being capable of detecting errors at any point in the design process. Further, such a system should be capable of detecting multiple types of design errors. The system should be capable of backtracking to the source of an error when error symptoms are detected. The system should also suggest corrective action to address the root cause of the problem as opposed to patching errors to correct deficient or erroneous signals. This invention relates specifically to design error prediction, while the related divisional patent applications referenced above relate to design error detection and design error recovery, respectively.
SUMMARY OF THE INVENTION
To overcome the limitations in the related art described above, and to overcome other limitations that will become apparent upon reading and understanding the present application, the present invention is embodied in a system and method for predicting, detecting and recovering from design errors in integrated circuits such as, for example, microprocessors, microcontrollers, analog-to-digital converters, and digital signal processors. For purposes of this description, design errors include errors, such as, for example, errors introduced by improper or incorrect use of design tools, errors introduced by data conversion problems, errors introduced by misinterpretation of design specifications, errors introduced as a result of design methodology, and errors introduced as a result of incorrect or improper logic circuit design or simulation. The system and method of the present invention uses inferential reasoning with a probabilistic model, such as a Bayesian Belief Network (BBN), to predict, detect and recover from design errors at any point in the design process by using information about the current design in combination with historical design data and design error data from previous integrated circuit designs in classes of integrated circuits that are the same or similar as the current design. BBN s are belief based probabilistic models that are typically represented as Directed Acyclic Graphs (DAG) in which nodes represent variables, arcs signify the existence of direct causal influence between the linked variables, and the strengths of these influences are expressed by forward conditional probabilities.
Prediction, detection, and recovery from design errors are preferably based on a probabilistic comparison of conditions or error symptoms, predicted or detected in the current design, to similar or identical conditions or error symptoms associated with design errors identified in prior designs. In addition, the system and method of the present invention are capable of backtracking or rolling back through the design to the source of an error when conditions or error sym
DeFrank Edmond A.
International Business Machines - Corporation
Starks, Jr. Wilbert L.
Tyson Thomas E.
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