Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2005-10-04
2005-10-04
Homere, Jean R. (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S013000, C703S017000, C703S021000, C717S128000, C711S118000
Reexamination Certificate
active
06952664
ABSTRACT:
A system and methods for simulating the performance (e.g., miss rate) of one or more caches. A cache simulator comprises a segmented list of buffers, with each buffer configured to store a data identifier and an identifier of the buffer's segment. Data references, which may be copied from an operational cache, are applied to the list to conduct the simulation. Initial estimates of each cache's miss rate include the number of references that missed all segments of the list plus the hits in all segments not part of the cache. A correction factor is generated from the ratio of actual misses incurred by the operational cache to the estimated misses for a simulated cache of the same size as the operational cache. Final predictions are generated by multiplying the initial estimates by the correction factor. The size of the operational cache may be dynamically adjusted based on the final predictions.
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Bridge William H.
Lahiri Tirthankar
Loaiza Juan R.
Nithrakashyap Arvind
Ferris Fred
Homere Jean R.
Oracle International Corp.
Park Vaughan & Fleming LLP
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