System and method for phase-locked loop (PLL) for high-speed...

Details System and method for phase-locked loop (PLL) for high-speed... System and method for phase-locked loop (PLL) for high-speed...

2007-07-16

2010-02-09

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S016000, C331S046000, C331S057000, C331S060000, C331S10800D, C331S135000, C331S17700V, C375S375000, C375S376000

Reexamination Certificate

active

07659783

ABSTRACT:
A phase-locked loop (PLL) to provide clock generation for high-speed memory interface is presented as the innovate PLL (IPLL). The IPLL architecture is able to tolerate external long loop delay without deteriorating jitter performance. The IPLL comprises in part a common mode feedback circuit with a current mode approach, so as to minimize the effects of mismatch in charge-pump circuit, for instance. The voltage-controlled oscillator (VCO) of the IPLL is designed using a mutually interpolating technique generating a 50% duty clock output, beneficial to high-speed double data rate applications. The IPLL further comprises loop filter voltages that are directly connected to each VCO cell of the IPLL. Conventional voltage-to-current (V-I) converter between loop filter and VCO is hence not required. A tight distribution of VCO gain curves is therefore obtained for the present invention across process corners and varied temperatures.

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