System and method for phase-locked loop initialization

Details System and method for phase-locked loop initialization System and method for phase-locked loop initialization

2007-09-04

2007-09-04

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S00100A, C331SDIG002, C327S159000

Reexamination Certificate

active

11155245

ABSTRACT:
Devices, methods, and systems for initializing a phased-lock loop (PLL) circuit which prevents or reduces the occurrences of voltage-controlled oscillator (VCO) frequency exceeding a divider's maximum input frequency, thus preventing or reducing at least one cause of lock failure. Disclosed is a PLL circuit having logic circuitry configured to hold a PFD reference-signal input low and provide a divided reference-signal to a PFD feedback-signal input while an initialization signal is asserted. The PLL can be initialized without adding circuitry to a VCO input. By asserting an initialization signal, an input voltage to a voltage-controlled oscillator is attenuated. The initialization signal is adapted to gate inputs to and outputs from the phase-locked loop circuit.

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patent: 2003-069423 (2003-03-01), None

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