Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-11-04
2001-12-25
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S155000, C327S160000, C327S244000, C327S291000
Reexamination Certificate
active
06333653
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and method embodied in a clock controller for aligning clocks to free running phase holds and for starting, stopping and pulsing the clocks, and in particular to a clock controller for aligning a plurality of N:1 ratioed clocks to free running phase holds and for starting, stooping and pulsing the ratioed clocks in phase with a master clock.
2. Description of the Related Art
Microprocessors commonly use clock signals to drive a variety of logic circuits within the microprocessor. However, not every logic circuit in the microprocessor necessarily runs at the same clock frequency. Consequently, solutions such as using multiple separate clocks, or single clocks using multiple clock dividers or multipliers and phase lock loops (PLL s) have been used to generate a range of clock frequencies to drive the various logic circuits within the microprocessor.
As the complexity and especially the speed of microprocessors and logic elements has increased, the need for clocks that have better phase alignment between sub-clocks generated by a master clock has also increased. Because the performance of microprocessor circuits can increase as the speed and alignment of clock signals improves, there is a clear need for better phase alignment between clock signals running at various frequencies within the microprocessor. Therefore, what is needed is a system and method for phase alignment of a plurality of clock frequencies, or sub-clocks, that allows the sub-docks to be started, stopped, or pulsed in phase with a master clock.
SUMMARY OF THE INVENTION
To overcome the limitations in the related art described above, and to overcome other limitations that will become apparent upon reading and understanding the present application, the present invention is embodied in a clock controller for generating a plurality of phase aligned sub-clocks and for allowing the sub-clocks to be started, stopped, or pulsed in phase with a master clock.
In general, the system and method of the present invention achieves control of the phase alignment of a plurality of ratioed sub-clocks when starting, stopping, and pulsing the sub-clocks. A master clock is preferably input to a clock splitter to provide a plurality of slave clocks. Phase holds, generated by decoding the count of a looping counter, are then used to gate or mask each of the slave clocks to produce ratioed clocks that produce phase aligned clock pulses at lower frequencies which are preferably integer factors of the master clock frequency. Commands to start, stop, or pulse the ratioed clocks may be issued to the clock controller.
Specifically, a plurality of N:1 phase holds are preferably produced by decoding the output of a looping counter. N is preferably an integer value, such that the phase holds may have values such as 1:1, 2:1, 3:1, 4:1, etc. The phase holds are then preferably used to gate the slave clocks to produce a plurality of N:1 ratioed clocks. For example, where N is equal to 2, a 2:1 phase hold is used to gate the slave clock such that for every two clock pulses of the slave clock, a single clock pulse is produced by the 2:1 ratioed clock.
Further, each N:1 rafioed clock is naturally phase aligned with the slave clock with which it is associated because the slave clock is simply gated by the associated phase hold. In addition, because the slave clocks are duplicates of the master clock, each of the ratioed clocks are also naturally phase aligned with the master clock. Therefore, because each of the ratioed clocks is phase aligned with the master clock, they are phase aligned with each other.
Because N is preferably an integer, for each set of ratioed clocks, an integer value M exists such that the N values of each of the ratioed clocks are common denominators of M. As a result, each of the ratioed clocks preferably generates a phase aligned clock pulse simultaneously for every M counts of the looping counter, with the first clock pulse of each ratioed clock occurring at count 0. Further, a total of M÷N clock pulses are preferably generated for each ratioed clock for each M counts of the looping counter.
For example, if M is 12 and one N is 3, the 3:1 ratioed clock will generate a total of 4 clock pulses (12÷3=4) for every 12 counts of the looping counter, starting at count 0, and repeating at count 3, count 6, and count 9 of the looping counter. Count 12 is effectively the same as count 0, as count 0 to count 11 completes one cycle of twelve counts. Further, the looping counter preferably counts to an integer multiple of M so that the state of ratioed clocks may be controlled when sending multiple pulse commands, or start or stop commands either before or after pulse commands to the clock controller.
Precise control of the ratioed clocks is preferably managed by ensuring that each of the phase holds is in the correct alignment when the start, stop, or pulse command is executed. Correct alignment of the phase holds is preferably managed by a function controlled shadow counter which either counts in synchronicity with the master clock, holds the count, or pulses the count depending upon whether a start, stop or pulse command has been issued to the clock controller.
Further, in one embodiment, the clock controller is preferably capable of entering an energy saving mode wherein the shadow counter counts at any integer denominator S of the looping counter, such that the number of clock pulses generated by the ratioed clocks will be divided by S. For example, in the energy saving mode, where the looping counter counts 12 cycles, and S is also equal to 12, the ratioed clocks preferably each generate one clock pulse for every twelve clock pulses that would have been generated by each ratioed clock when the clock controller was not in an energy saving mode. Therefore, any logic circuits or microprocessors driven by the clock controller will use significantly less energy, as they will run at one-twelfth their normal operating speed.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings wherein like reference numbers represent like parts of the invention.
REFERENCES:
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5945862 (1999-08-01), Donnelly et al.
patent: 5999027 (1999-12-01), Yamazaki
patent: 6044122 (2000-03-01), Ellersick et al.
patent: 6067334 (2000-05-01), Bostica et al.
Floyd Michael Stephen
Reick Kevin F.
Skergan Timothy Michael
Callahan Timothy P.
DeFrank Edmond A.
Emile Volel
International Business Machines - Corporation
Luu An T.
LandOfFree
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