Multiplex communications – Channel assignment techniques – Using a separate control line or bus for access control
Reexamination Certificate
1999-01-25
2002-05-14
Chin, Wellington (Department: 2731)
Multiplex communications
Channel assignment techniques
Using a separate control line or bus for access control
C370S489000
Reexamination Certificate
active
06389033
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the transfer of signals between a codec and a codec controller through an interconnecting bus, and specifically to a system and method for performing signal acceleration on an AC-link bus.
2. Description of Related Art
Personal computers are currently being used for a wide variety of multimedia applications, where it is now becoming desirable for personal computers (PCs) to function with high quality audio performance. Current PC audio architectures are designed to run midrange audio-performance-integrated ISA products. In order to provide PCs with high performance / high quality audio comparable to electronics devices, a new PC architecture capable of providing this performance needed to be developed. Thus, a computer industry consortium developed a new PC audio architecture, the Audio Codec '97 (AC '97), for next-generation audio-intensive PC applications, such as DVD, 3-D multiplayer games, and interactive music. The AC '97 architecture defines a high quality audio architecture for a PC platform to support a wide range of high quality audio solutions, from a 2-channel mix of digital and analog audio inside the PC to multi-channel audio outside the PC. The AC '97 includes at least one codec and codec controller. The codec includes two separate chips, one for primarily analog applications and one for primarily digital applications. By separating the functions performed between the analog and digital chips, individual yields can be improved which lead to overall cost reduction for the system.
The codec performs digital-to-analog conversion (DAC) and analog-to-digital conversion (ADC), mixing, analog processing, and modem codec functions. The codec functions as a slave to a digital codec controller, which, in turn, is connected to the CPU of the PC, as shown in FIG.
1
. The codec communicates with the codec controller through a digital serial link, referred to as the AC-link bus. The codec performs the appropriate data conversion and communicates analog signals to an input/output device. The AC-link bus was specifically designed to directly connect the codec to the codec controller. In prior PC architectures, it was necessary to connect an interface device between a codec and the core logic controlling the codec. The AC '97 eliminates the need for a separate interface device to be incorporated by utilizing the AC-link bus to directly connect the codec to the codec controller.
The AC-link bus is a bi-directional, 5-wire, serial time-division multiplexed (TDM) interface designed for a dedicated point-to-point interconnect, as illustrated in FIG.
2
. All digital audio streams, modem line codec streams, and command/status information are communicated over the AC-link bus in data packets. The AC-link bus architecture has a defined protocol which divides each data packet into 12 outgoing and 12 incoming data streams. Each of the data streams are positioned in a respective one of the 12 TDM slots in the data packet, as shown in FIG.
3
. The output data streams correspond to the multiplexed bundles of all digital output data targeting the codec's DAC inputs and control registers.
The industry consortium developing the AC '97 architecture wanted to promote interoperability between codecs and codec controllers produced by different vendors to function according to AC-link protocol. Thus, strict adherence to the specified audio input and output frame slot definitions, AC-link bus protocol, and electrical timings are required for interoperability to be maintained between various codecs and codec controllers. The AC-link bus basically performs one function, it transmits the data streams in the data packets defined by the AC-link protocol between the codec controller and the codec, so that the AC-link bus merely provides a direct data link between the codec and the codec controller.
No significant data manipulation can be performed on the data streams communicated through the AC-link bus defined by the industry consortium. If it is desirous to manipulate any of the data streams in a data packet, it is necessary to send the data packet through the codec controller to the host CPU of the PC where a data manipulation algorithm can perform the desired function. There are many types of data applications which require hardware acceleration, including Head Related Transfer Function (HRTF) algorithms, AC3 decode, MPEG decode, music synthesis, downloadable sound (DLS) synthesis assistance, encryption/decryption, reverb, modulation/demodulation, security protocol, compression/decompression, filtering, adding delays or special effects, and any communication protocol. These acceleration functions typically require signal processing or data manipulation algorithms to be performed by the host CPU. After performing the desired acceleration function, the processed signal must then be transmitted back through the codec controller, through the AC-link, and to the codec, where it is transmitted to the respective input/output device. However, requiring the host CPU to perform signal acceleration functions can be inefficient, since certain signal acceleration applications require real-time access to the data in order to function properly. The architecture of the AC '97 set forth by the industry consortium does not define such real-time data manipulation to be performed on signals transmitted across the AC-link bus.
There is clearly a need for a system and method for performing signal acceleration on the data streams of data packets transmitted over an AC-link bus directly in a real time manner. Moreover, there is a need for a system and method for performing signal acceleration on the data streams of data packets transmitted over an AC-link bus in a flexible and efficient manner without having to send the data streams through the codec controller to a host CPU to perform the desired acceleration function.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to overcome the aforementioned shortcomings associated with the prior art.
The present invention provides a system and method for performing real-time signal acceleration of data streams communicated over an AC-link bus.
These as well as additional advantages of the present invention are achieved by providing a system and method for performing signal acceleration on an AC-link bus by positioning an accelerator directly in the communication path of the AC-link bus situated between a codec and its respective codec controller. The codec connected to the AC-link bus is configured for a particular AC-link bus protocol, so that the codec recognizes which type of data stream appears in a data packet received over the AC-link bus. Currently, the AC-link bus protocol defines twelve (12) TDM data slots, where each data slot is assigned a respective data stream accomplishing a particular function with one of the data slots containing TAG information about the data packet. The codec then performs any necessary data conversion and transmits the data appearing in a particular TDM slot to an associated input/output device. The accelerator is connected to the AC-link bus such that signal processing or data manipulation is performed by the accelerator on the data packets communicated across the AC-link bus, and the processed data packets are transmitted to one or multiple codecs according the same communication protocol.
The accelerator is connected between a codec and its respective codec controller, so that the accelerator is arranged to receive signals traveling through the AC-link bus. This allows the accelerator to have real-time access to the input and output data streams traveling through the AC-link bus, so that signal processing or data manipulation can be performed without multiple communications to the codec controller or host computer CPU.
REFERENCES:
patent: 5642422 (1997-06-01), Hon et al.
patent: 6122220 (2000-09-01), Kim et al.
patent: 6122697 (2000-09-01), Potts
patent: 6147522 (2000-11-01), Rhode e
Braun David P.
Maxwell Conrad A.
Sneed George C.
Chin Wellington
Conexant Systems Inc.
Lyon & Lyon LLP
Pham Brenda
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