Television – Bandwidth reduction system – Data rate reduction
Patent
1997-08-11
1999-10-26
Casler, Brian L.
Television
Bandwidth reduction system
Data rate reduction
348699, 348413, 348420, H04N 730
Patent
active
059737425
ABSTRACT:
A system and method for estimating motion vectors between frames of a video sequence which operates with reduced memory loading latency according to the present embodiment. The motion estimation system includes a motion port pixel processing array according to the present embodiment. The processing array includes a reference block memory array for storing a reference block and a candidate block memory array for storing a candidate block. According to the present embodiment, each of the reference block memory array and candidate block memory array are configured with dual ports to a reference block memory and a search window memory. Each of the reference block memory array and candidate block memory array are further configured to allow dual port loading during the entire initialization sequence, when one or more of either a reference block or candidate block is being loaded into the respective memory array. During initialization or loading, memory elements for each of the reference block and candidate block are loaded in parallel according to the present embodiment. This reduces the clock latency of the initial loading of the memory array as well as subsequent loadings of a new candidate block for each column of the search window. This reduces the loading to half the number of cycles as compared with prior art methods. The present embodiment thus efficiently performs motion estimation with reduced memory array loading latency. The processing array of the present embodiment is also capable of operating in either frame mode or field mode.
REFERENCES:
patent: 5030953 (1991-07-01), Chiang
patent: 5512962 (1996-04-01), Homma
patent: 5550591 (1996-08-01), Rim et al.
patent: 5557332 (1996-09-01), Koyanagi et al.
patent: 5568203 (1996-10-01), Lee
Gardyne Robert
Khazeni Anoush
Casler Brian L.
Din Luanne P.
LSI Logic Corporation
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