System and method for performing efficient random write operatio

Details System and method for performing efficient random write operatio System and method for performing efficient random write operatio

1995-04-19

1997-10-14

Lall, Parshotam S.

395872, G06F 1300

Patent

active

056780630

ABSTRACT:
A system and method for rapidly transferring large amounts of small-sized data to non-sequential addresses in an instumentation system. According to a preferred embodiment, a host computer includes a plurality of test vectors stored in memory which control the operation of attached instruments. The host processor generates a block of address/data pairs in response to the test vectors, with each pair containing data and a destination address. This block is stored in memory and the address of the block is provided to a random write engine. The random write engine then distributes the data to the respective instruments at the proper addresses with minimal processor invention. Therefore, large amounts of small-sized data may be rapidly transferred to non-sequential addresses without burdening the processor.

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patent: 5263142 (1993-11-01), Watkins et al.
patent: 5499384 (1996-03-01), Lentz et al.
MC689440, Dual-Channel Direct Memory Access Controller, Motorola Semiconductor Products Inc., Austin, Texas, Feb., 1984, pp. 1-10 through 8-4, Foldout 1-8.

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