Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2006-08-28
2010-10-19
Kindred, Alford W (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S004000, C712S008000, C712S022000, C712S222000
Reexamination Certificate
active
07818539
ABSTRACT:
A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed are divided into two groups based on whether or not they satisfy a given condition by e.g., steering each to one of the two index vectors. Once the data have been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication. Other examples of conditional operations include combining one or more input vectors into a single output vector based on a condition vector, conditional vector switching, conditional vector combining, and conditional vector load balancing.
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Dally William J.
Kapasi Ujval J.
Owens John D.
Rixner Scott
Crawford & Maunu PLLC
Dews Brooke J
Kindred Alford W
The Board of Trustees of the Leland Stanford Junior University
The Massachusetts Institute of Technology
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