Computer graphics processing and selective visual display system – Computer graphic processing system – Interface
Reexamination Certificate
1998-03-31
2001-04-03
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Interface
C345S506000, C345S522000, C708S607000
Reexamination Certificate
active
06211892
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to the field of computer systems, and in particular, to an apparatus and method for performing multi-dimensional computations based on an intra-add operation.
2. Description of the Related Art
To improve the efficiency of multimedia applications, as well as other applications with similar characteristics, a Single Instruction, Multiple Data (SIMD) architecture has been implemented in computer systems to enable one instruction to operate on several operands simultaneously, rather than on a single operand. In particular, SIMD architectures take advantage of packing many data elements within one register or memory location. With parallel hardware execution, multiple operations can be performed with one instruction, resulting in significant performance improvement.
Currently, the SIMD addition operation only performs “vertical” or inter-register addition, where pairs of data elements, for example, a first element Xn (where n is an integer) from one operand, and a second element Yn from a second operand, are added together. An example of such a vertical addition operation is shown in Table 1, where the instruction is performed on the sets of data elements (a
1
and a
2
) and (b
1
and b
2
) accessed as Source1 and Source2, respectively.
TABLE 1
Although many applications currently in use can take advantage of such a vertical add operation, there are a number of important applications that require the rearrangement of the data elements before the vertical add operation can be implemented so as to provide realization of the application.
For example, a matrix multiplication operation is shown below:
MATRIX
A
*
VECTOR
X
=
VECTOR
Y
ROW
1
ROW
2
ROW
3
ROW
4
[
A
11
A
12
A
13
A
14
A
21
A
22
A
23
A
24
A
31
A
32
A
33
A
34
A
41
A
42
A
43
A
44
]
×
[
X
1
X
2
X
3
X
4
]
=
[
A
11
X
1
+
A
12
X
2
+
A
13
X
3
+
A
14
X
4
A
21
X
1
+
A
22
X
2
+
A
23
X
3
+
A
24
X
4
A
31
X
1
+
A
32
X
2
+
A
33
X
3
+
A
34
X
4
A
41
X
1
+
A
42
X
2
+
A
43
X
3
+
A
44
X
4
]
To obtain the product of a matrix A with a vector X to obtain the resulting vector Y, instructions are used to: 1) store the columns of the matrix A as packed operands (this typically requires rearrangement of data because the rows of the matrix A coefficients are stored to be accessed as packed data operands, not as columns); 2) store a set of packed operands that each have a different one of the vector X coefficients in every data element; 3) use vertical multiplication as shown in Tables 2A-2D; and 3) use vertical adds as shown in Tables 2E-2G.
TABLE 2A
TABLE 2B
TABLE 2C
TABLE 2D
TABLE 2E
TABLE 2F
TABLE 2G
Accordingly, there is a need in the technology for a method and operation for increasing code density by eliminating the need for the rearrangement of data elements and the corresponding rearrangement operations.
BRIEF SUMMARY OF THE INVENTION
An apparatus and method for performing an intra-add operation on packed data using computer-implemented steps is described. A processor is coupled to a hardware unit which transmits data representing graphics to another computer or display. A storage device coupled to the processor, has stored therein a routine, which, when executed by the processor, causes the processor to generate the data. The routine causes the processor to at least access a first packed data operand having at least one pair of data elements; swap positions of the data elements within the at least one pair of data elements to generate a second packed data operand, add data elements starting at the same bit positions from the first and second packed data operands to generate a third packed data operand.
REFERENCES:
patent: 5390135 (1995-02-01), Lee et al.
patent: 5677862 (1997-10-01), Peleg et al.
patent: 5815421 (1998-09-01), Dulong et al.
patent: 5819117 (1998-10-01), Hansen
patent: 5822232 (1998-10-01), Dulong et al.
patent: 5862067 (1999-01-01), Mennemeier et al.
patent: 5875355 (1999-02-01), Sidwell et al.
patent: 5883824 (1999-03-01), Lee et al.
patent: 6006316 (1999-12-01), Dinkjian
patent: 6014684 (2000-01-01), Hoffman
patent: 6115812 (2000-09-01), Abdallah et al.
J.F.Takie, et al., “Comparison Of Some Parallel Matrix Multiplication Algorithms”, 8th Mediterranean Electrotechnical Conference, Melecon'96, vol. 1, 1996, pp. 155-158.*
H. Barad, et al., “Intel's Multimedia Architecture Extension”, Nineteenth Conventio Of Electrical And Electronics Engineers In Israel, 1996, pp. 148-151.*
Visual Instruction Set (VIS™) User's Guide, Sun Microsystems, Version 1.1, Mar. 1997.
AMD-3D Technology Manual, AMD, Publication No.: 21928, Issued Date: Feb. 1998.
Huff Thomas
Thakkar Shreekant S.
Blakely , Sokoloff, Taylor & Zafman LLP
Chauhan Ulka J.
Intel Corporation
LandOfFree
System and method for performing an intra-add operation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for performing an intra-add operation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for performing an intra-add operation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2438180