Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Reexamination Certificate
2002-07-19
2004-11-09
Callahan, Timothy P. (Department: 2816)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
C375S375000
Reexamination Certificate
active
06816018
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to clock synchronization. More specifically, it relates to partitioning phase-locked loops.
BACKGROUND OF THE INVENTION
In data transmission, for example, two systems may communicate to exchange information. While data transmission may be performed using either analog or digital systems, digital systems are commonly employed in applications such as, computer systems, telecommunications systems and other systems. For digital systems, data is typically encoded into discrete values and may be transmitted using a variety of different protocols. The various transmission protocols can specify transmission characteristics, such as signaling methods, framing methods, data rates and other characteristics.
In order to properly send and receive signals, a transmitter and receiver should generally send and receive data at the same frequency. By using the same frequencies, the receiver can accurately align with the transmitter and read the incoming signal at the proper times. The frequency of operation, and thus the alignment of the transmitter and receiver, is generally controlled by a system timing reference, such as a clock.
If the clock frequencies of the transmitter and receiver are off, then gradually over time the receiver strays from reading the signal at the correct point. As the timing error between the devices grows, the receiver may begin to incorrectly read the incoming signals. This can cause an error in receiving the transmitted data and, therefore, is undesirable.
One way to closely align the clocks of two digital systems is for each system to use a clock at approximately the same frequency or at multiples of each other. This, however, is not always an adequate solution, because the oscillators used to produce the clocks cannot be manufactured to be exact multiples of each other. Since, this method cannot support continuous data transmission without errors, the transmitter and receiver must periodically stop exchanging data in order to realign their clocks. Also, highly accurate oscillators are expensive, and requiring each component to include its own highly accurate oscillator can significantly increase the system's cost.
A second way of matching two digital systems is for only one system to produce a clock and for that system to provide the other system with the clock, a process that is generally termed synchronous communication. Sharing a clock, however, may not precisely synchronize the two systems. When a signal is transmitted along a transmission medium, the signal can be affected by the medium's impedance. As the signal travels a longer distance, the transmission medium can have a greater affect on the resulting signal. Thus, the resulting signal changes from the original signal. Additionally, devices connected to the transmission mediums may also alter the signals traveling between the devices, and other signals traveling in proximity may produce interference that alters the shared signal. Therefore, the received clock signal from another system may not necessarily match the clock signal actually transmitted by the other system.
A third way of matching two digital systems is for both systems to produce a clock and for one system to synchronize its clock with the clock of the other system. One way to synchronize two clocks is by using a phase-locked loop (“PLL”). A PLL can be used to lock an outputted clock signal to the frequency of an inputted timing reference. To synchronize two systems, the clock in one system can be produced independently, and the clock in the other system can be produced using a PLL. The independent clock of the first system can be used as the timing reference inputted to the PLL. Alternatively, timing information extracted from a received data signal may be used as a timing reference. Then, the output of the PLL can be locked to the inputted timing reference.
In many systems it may be desirable to synchronize a PLL-generated clock to any one of multiple possible reference inputs from other sources. In one method of using multiple reference inputs, the reference inputs may connect to respective cards. Each respective card may include the complete PLL circuitry to produce a locked signal. The locked signal can then be provided to other devices for use as a timing reference. This implementation, however, can require additional and duplicated circuitry on each card. Also, including a VCO on each card can additionally increase the cost of the cards.
In another method of using multiple reference inputs, the reference inputs can each be provided to a different card. The cards can each include a phase comparator, and the output of the phase comparator of each card links over a dedicated connection to a common VCO. The use of dedicated connections requires additional circuitry within the system to support multiple reference inputs. It also requires advanced knowledge of the sources of the various timing references in order to provide all the necessary dedicated connections, and this does not allow for the design of the system to be easily changed. Further, since all the phase comparators connect to the VCO, one phase comparator must be selected for use with the VCO, and the other phase comparators must be disabled to prevent their output from interfering with the operation of the VCO.
Therefore, there exists a need for an improved method and system for handling multiple timing references in a phase-locked loop.
SUMMARY OF THE INVENTION
In a phase-locked loop, a reference signal can be provided to the phase comparator. The phase comparator can produce a phase error signal based on the reference signal and based on a feedback signal. Multiple cards may each include the phase comparator circuitry. One or more of the phase error signals produced by the device cards may be transmitted across a data link, such as a bus, to a controlled oscillator.
The controlled oscillator may use a received phase error signal to produce an output, and the output may oscillate at a multiple of the reference signal from one of the device cards. The output of the controlled oscillator may be provided to the device cards, such as for use as a timing signal. The output of the controlled oscillator may also be provided to the multiple device cards to be used as the feedback signal in their respective phase comparator circuitry.
These as well as other aspects and advantages of the present invention will become apparent from reading the following detailed description, with appropriate reference to the accompanying drawings.
REFERENCES:
patent: 4641146 (1987-02-01), Gehman
patent: 4890305 (1989-12-01), Devries
patent: 4893097 (1990-01-01), Zwack
patent: 5148450 (1992-09-01), Hollyer
patent: 5446767 (1995-08-01), Nakagawa et al.
patent: 5459766 (1995-10-01), Huizer et al.
patent: 5488641 (1996-01-01), Ozkan
patent: 5515403 (1996-05-01), Sloan et al.
patent: 5548249 (1996-08-01), Sumita et al.
patent: 5790608 (1998-08-01), Benayoun et al.
patent: 5990673 (1999-11-01), Forsberg
patent: 5999025 (1999-12-01), New
patent: 6078595 (2000-06-01), Jones et al.
patent: 6091932 (2000-07-01), Langlais
patent: 6166572 (2000-12-01), Yamaoka
patent: 6285172 (2001-09-01), Torbey
patent: 6470032 (2002-10-01), Dudziak et al.
patent: 6539799 (2003-04-01), Handrich et al.
LeVieux John C.
Trumbo Bruce L.
3Com Corporation
Callahan Timothy P.
Cox Cassandra
McDonnell Boehnen & Hulbert & Berghoff LLP
LandOfFree
System and method for partitioning a system timing reference... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for partitioning a system timing reference..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for partitioning a system timing reference... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3363830